Data Sheet

AD3530/AD3530R

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. 0 | 9 of 45

Figure 5. WLCSP Pin Configuration

Table 8. Pin Function Descriptions

Pin No.

Mnemonic

Type1

Description

A1

MUX_OUT

AO

Analog Multiplexer. The MUX_OUT pin is used to monitor the internal die temperature, output voltages, and output current of a

selected channel.

B1, B2, D2

VDD

S

Power Supply Input. The AD3530/AD3530R operate from 2.7V to 5.5V. Decouple the VDD supply with a 10µF capacitor in parallel

with a 0.1µF capacitor to GND.

C3

IOVDD

DI

Digital Power Supply. The voltage on the IOVDD pin is specified in the Table 2 section.

B3, C1, C2,

D3, E1

GND

S

Ground Reference Point for All Circuitry on the Device.

D1

VREF

AI/O

Reference Output Voltage. When using the internal reference, this is the reference output pin. The VREF is the reference input by

default.

E2

VOUT7

AO

Analog Output Voltage from DAC 7. The output amplifier has rail-to-rail operation.

E3

VOUT6

AO

Analog Output Voltage from DAC 6. The output amplifier has rail-to-rail operation.

E4

VOUT5

AO

Analog Output Voltage from DAC 5. The output amplifier has rail-to-rail operation.

D4

VOUT4

AO

Analog Output Voltage from DAC 4. The output amplifier has rail-to-rail operation.

E5

SDI

DI

Serial Data Input. Logic input. Provides data to be written to the device and is clocked into the register on the rising edge of SCLK.

D5

CSB

DI

Active-Low Control Input. This is the frame synchronization signal for the input data.

C4

RESETB

DI

Asynchronous Reset pin. Active-low logic input and falling edge sensitive. See the Hardware Reset section for additional

information.

C5

SDO

DO

Serial Data Output. Logic output. A readback operation provides data on this output pin as a serial data stream. Data is clocked out

on the falling edge of SCLK and is valid on the rising edge of SCLK.

B5

SCLK

DI

Serial Clock Input. Data transfers at rates of up to 50MHz for write and read operations.

A5

LDACB

DI

Asynchronous Load DAC pin. Active-low logic input, falling edge sensitive. See the Hardware LDAC section for additional

information.

B4

VOUT0

AO

Analog Output Voltage from DAC 0. The output amplifier has rail-to-rail operation.

A4

VOUT1

AO

Analog Output Voltage from DAC 1. The output amplifier has rail-to-rail operation.

A3

VOUT2

AO

Analog Output Voltage from DAC 2. The output amplifier has rail-to-rail operation.

A2

VOUT3

AO

Analog Output Voltage from DAC 3. The output amplifier has rail-to-rail operation.

1 AO is analog output pin, AI/O is analog input or output pin, S is supply pin, DI is the digital input pin, and DO is the digital input pin.