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AD3530 数据表(PDF) 29 Page - Analog Devices

部件名 AD3530
功能描述  8-Channel, 16-Bit Voltage Output DACs, On-Chip Reference, SPI
PDF  45 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD3530 数据表(HTML) 29 Page - Analog Devices

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Data Sheet
AD3530/AD3530R
REGISTERS SUMMARY
analog.com
Rev. 0 | 29 of 45
Table 10. AD3530/AD3530R Register Summary
Reg
Name
Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
RW
0x00
INTERFACE_CO
NFIG_A
[7:0]
SW_RESET RESERVED
ADDR_ASC
ENSION
SDO_ENAB
LE
RESERVED
RESET_SW 0x10
R/W
0x01
INTERFACE_CO
NFIG_B
[7:0]
SINGLE_IN
ST
RESERVED
SHORT_INS
TRUCTION
RESERVED
0x00
R/W
0x02
DEVICE_CONFI
G
[7:0]
RESERVED
OPERATING_MODES
0x00
R/W
0x03
CHIP_TYPE
[7:0]
RESERVED
CHIP_TYPE
0x08
R
0x04
PRODUCT_ID_L [7:0]
PRODUCT_ID[7:0]
0x01
R
0x05
PRODUCT_ID_H [7:0]
PRODUCT_ID[15:8]
0x00
R
0x06
CHIP_GRADE
[7:0]
GRADE
DEVICE_REVISION
0x01
R
0x0A SCRATCH_PAD
[7:0]
SCRATCH_PAD
0x00
R/W
0x0B SPI_REVISION
[7:0]
SPI_TYPE
VERSION
0x84
R
0x0C VENDOR_L
[7:0]
VID[7:0]
0x56
R
0x0D VENDOR_H
[7:0]
VID[15:8]
0x04
R
0x0E STREAM_MODE [7:0]
LOOP_COUNT
0x00
R/W
0x0F
TRANSFER_CO
NFIG
[7:0]
RESERVED
KEEP_STR
EAM_LENG
TH_VAL
RESERVED
0x00
R/W
0x10
INTERFACE_CO
NFIG_C
[7:0]
CRC_ENABLE
STRICT_RE
GISTER_AC
CESS
RESERVED
ACTIVE_INTERFACE_MO
DE
CRC_ENABLEB
0x23
R/W
0x11
INTERFACE_ST
ATUS_A
[7:0]
NOT_READ
Y_ERR
RESERVED
CLOCK_CO
UNT_ERR
CRC_ERR
RESERVED
REGISTER_
PARTIAL_A
CCESS_ER
R
RESERVED 0x00
R/W
0x20
OUTPUT_OPER
ATING_MODE_0 [7:0]
MODE_CH_3
MODE_CH_2
MODE_CH_1
MODE_CH_0
0xFF
R/W
0x21
OUTPUT_OPER
ATING_MODE_1 [7:0]
MODE_CH_7
MODE_CH_6
MODE_CH_5
MODE_CH_4
0xFF
R/W
0x2A
OUTPUT_CONT
ROL_0
[7:0]
RESERVED
RANGE
RESERVED
0x00
R/W
0x3C
REFERENCE_C
ONTROL_0
[7:0]
RESERVED
SEL
0x00
R/W
0x93
MUX_OUT_SEL
ECT_0
[7:0]
RESERVED
SEL
0x00
R/W
0xC2
STATUS_CONTR
OL
[7:0]
RESERVED
UPDATE_E
RR
RESET_WA
RNING
INTERFACE
_ERR
RESERVED 0x04
R/W
0xD0 HW_LDAC_EN_0 [7:0]
HLD_EN_C
H_7
HLD_EN_C
H_6
HLD_EN_C
H_5
HLD_EN_C
H_4
HLD_EN_C
H_3
HLD_EN_C
H_2
HLD_EN_C
H_1
HLD_EN_C
H_0
0xFF
R/W
0xD1 SW_LDAC_EN_0 [7:0]
SLD_EN_C
H_7
SLD_EN_C
H_6
SLD_EN_C
H_5
SLD_EN_C
H_4
SLD_EN_C
H_3
SLD_EN_C
H_2
SLD_EN_C
H_1
SLD_EN_C
H_0
0xFF
R/W
0xD3
TO
0xE1
by 21
DAC_CHn
[15:8]
DAC_VAL[15:8]
0x0000
R/W
[7:0]
DAC_VAL[7:0]
0xE31 MULTI_DAC_CH
[15:8]
MULTI_DAC_VAL[15:8]
0x0000
R/W
[7:0]
MULTI_DAC_VAL[7:0]
0xE4
MULTI_DAC_SE
L_0
[7:0]
MD_SEL_C
H_7
MD_SEL_C
H_6
MD_SEL_C
H_5
MD_SEL_C
H_4
MD_SEL_C
H_3
MD_SEL_C
H_2
MD_SEL_C
H_1
MD_SEL_C
H_0
0xFF
R/W
0xE5
SW_LDAC_TRIG
_0
[7:0]
SLD_TRIG_
0
RESERVED
0x00
R/W



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