AD3530 datasheet(21/45 Pages) AD

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Data Sheet

AD3530/AD3530R

THEORY OF OPERATION

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Rev. 0 | 21 of 45

where:

VMEAS is the measured voltage output of the selected channel.

MUX_OUT is the voltage output on the MUX_OUT pin in volts.

The transfer function when using current output monitor:

IMEAS = MUX_OUT × 40 mA/V (4)

where:

IMEAS is the measured current at the output of the selected channel.

MUX_OUT is the voltage output on the MUX_OUT pin in volts.

The internal die temperature can also be monitored through the

MUX_OUT pin by setting the MUX_OUT_SELECT(SEL) to 0x19.

The transfer function used to derive the measured temperature with

internal reference enabled is given by the following equation:

TMEAS=MUX_OUT − 0.44

0.0016 V/°C

(5)

where:

TMEAS is the measured internal die temperature in °C.

MUX_OUT is the voltage at the MUX_OUT pin in volts.

The integrated multiplexer has a buffered output capable of provid-

ing of ±5mA current. The errors of monitoring the VOUTn and

IOUTn, where n is the channel number, are typically ±5mV and

±2mA, respectively.

DAC CORE FUNCTIONS

Each DAC channel has its own Input Register and DAC Register,

as shown in Figure 59. Both registers are accessible through the

serial interface. The DAC register stores digital code equivalent to

the DAC output voltage while the input register acts as a temporary

staging register before being passed on the DAC Register. With

the LDAC function, one or more DAC registers could be updated in

parallel with the data held in the input register.

The DAC registers can be written to directly, in which case the

corresponding output updates immediately without the need for a

hardware or software LDAC. Directly writing to the DAC register

does not affect the data stored in the input register.

Writing to the MULTI_INPUT_CH register allows one or more input

registers to be updated in a single write operation. The MULTI_IN-

PUT_SEL_0 register determines which input register will be updat-

ed with the data written to the multiple input register. See the

Multiple Input Select 0 Register section for additional information.

Similarly, writing to the MULTI_DAC_CH register allows one or

more DAC registers to be updated in a single write operation.

MULTI_DAC_INPUT_SEL_0 determines which DAC register will be

updated with the data written to the multiple DAC register. See the

Multiple DAC Select 0 Register section for more information.

To ensure that the DAC update is successful, DAC register updates

should only occur once every 640ns. Refer to tL2 and tL3 from Table

5. An error flag will also be asserted when a DAC update write is

unsuccessful which can be check by reading the UPDATE_ERR bit

on the Status Control Register.

LDAC Function

The LDAC function is used to initiate the transfer of the contents of

select input registers to the corresponding DAC registers, thereby

updating one or more VOUT pins at the same time. The LDAC

function can be executed by hardware through the LDACB pin or

by software through SW_LDAC_TRIG_A or SW_LDAC_TRIG_B

registers. Both hardware and software LDAC perform the same

function.

Hardware LDAC

The AD3530/AD3530R have active low LDACB pins that are falling

edge sensitive. If the LDACB signal is brought low, the selected in-

put register contents are transferred to corresponding DAC register.

If LDACB is held low when writing to the device, the input registers

appear transparent, and when an input register is written to, the

DAC register is updated with the contents of the input register at the

same time. When LDACB is held high, DAC codes can be written to

any input registers without affecting the DAC output. Refer to Figure

The Hardware LDAC Enable 0 Register is used to determine the

DAC channels to be updated from the corresponding input registers

when LDACB is active or asserted. By default, all DAC channels

are selected and the HLD_EN_CH_n bitfields contain a 1. A 0 set

on a HLD_EN_CH_n bitfield disables the hardware LDAC feature

for the target DAC channel.

Software LDAC

The software LDAC function is synonymous to an LDACB falling

edge. It provides a way to initiate a transfer of content between

selected input registers to DAC registers through the serial interface

via writing 1 to the SLD_TRIG_A bit on the Software LDAC Trigger

0 Register or to the SLD_TRIG_B bit on the Software LDAC Trigger

0 Register.

The Software LDAC Enable 0 Register is used to determine the

DAC channels to be updated from the corresponding input registers

when a software LDAC is performed. By default, all DAC channels

are selected and the SLD_EN_CH_n bitfields contain a 1. A 0 set

in a SLD_EN_CH_n bitfield disables the software LDAC feature for

the target DAC channel.

POWER-ON RESET

On power-up the input and DAC data registers of every DAC

channel are loaded with a zero code. Meanwhile, the POR circuit

ensures that the DAC output amplifiers are powered down (see

Mode 3 in the Modes of Operation section) until the output operat-

ing mode for the channel is changed. All registers are reset to their

default values.

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