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Data Sheet

AD3530/AD3530R

THEORY OF OPERATION

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DIGITAL-TO-ANALOG CONVERTER

The AD3530/AD3530R are low power, 8-channel, 16-bit, voltage

output DACs that operate on analog supply voltages of 2.7V to

5.5V and digital supply voltages of 1.08V to 1.98V. The AD3530/

AD3530R have 5ppm/°C 2.5V on-chip references.

The AD3530/AD3530R offer versatile 4-wire serial interfaces com-

patible with classic SPI. See the Serial Interface section for more

details.

DAC Channels

The AD3530/AD3530R contain 8 buffered voltage output DAC

channels capable of sourcing 50mA and sinking 40mA of current. A

simplified block diagram of a DAC channel is shown in Figure 59.

The output amplifier generates rail-to-rail voltages on its output,

giving an ideal output range of 0 to VREF at OUTPUT_CON-

TROL_0(RANGE) = 0 (VDD > VREF), or 0 to 2 × VREF at

OUTPUT_CONTROL_0(RANGE) = 1 (VDD > 2 × VREF). The

headroom and footroom voltages, which are defined by the output

current, should also be taken into consideration when selecting the

appropriate output range and VDD. The output slew rate is 1.1V/μs

with a typical ¼ to ¾ settling time of 5μs while driving a load of 2kΩ

in parallel with 200pF to GND.

Figure 59. DAC Channel Block Diagram

Transfer Function

The conversion of the digital input code to the ideal output voltage

is given by the following equation:

VOUTn=VREF×D2N×G

where:

VOUTn is the output voltage seen at the selected DAC channel n.

VREF is the voltage present on the VREF pin, which is an input by

default. When the internal reference is turned on, this is equal to

2.5V.

D is the decimal equivalent of the straight binary code that is loaded

into the DAC register (0 to 65535 for the AD3530/AD3530R).

N is the DAC resolution in bits.

G is the gain of the output amplifier. G = 1 if OUTPUT_CON-

TROL_0(RANGE) = 0 (default), and G = 2 if OUTPUT_CON-

TROL_0(RANGE) = 1.

Modes of Operation

There are four operating modes for each channel of the AD3530/

AD3530R as listed in Table 9. These operating modes are software

programmable via the MODE_CH_n[1:0] in the Output Operating

Mode 0 Register and the Output Operating Mode 1 Register. Upon

power-up or after a power-on reset, Operating Mode 3 is set

by default, where the output amplifier is powered down and an

effective resistance of 32kΩ can be seen from the VOUTn pin to

GND.

Table 9. AD3530/AD3530R Operating Modes

Operating Modes Output State

MODE_CH_n [1]

MODE_CH_n [0]

Normal operation

1kΩ to GND

7.7kΩ to GND

32kΩ (default)

Entering into Mode 1, Mode 2, or Mode 3 will not affect other

The input or DAC registers can still be updated but will not reflect

on the DAC output pins.

VOLTAGE REFERENCE

The AD3530R has an on-chip, buffered, 2.5V, 5ppm/°C reference

available at the VREF pin that is capable of sourcing external loads

up to +5mA.

By default, upon power-up or after a power-on reset, the VREF

pin is configured as an input pin, and external reference voltage

must be provided. The internal reference can be enabled by setting

REFERENCE_CONTROL_0(SEL) to 1. See the the Reference

Control 0 Register section for more details.

INTEGRATED MULTIPLEXER

The AD3530/AD3530R contain a 27:1 multiplexer that can output

a voltage on the MUX_OUT pin representative of either the output

voltage or output current of a chosen channel or the internal

die temperature of the device. The monitor point can be set by

configuring the SEL bits on the Multiplexer Input Select 0 Register.

An invalid write MUX_OUT_SELECT(SEL) will be ignored and the

MUX_OUT_SELECT(SEL) value should not change.

The transfer function of the integrated multiplexer when voltage

output monitor is selected is given by the equation below. A

voltage output of VREF represents the full scale range of the

DAC channel being monitored regardless of the OUTPUT_CON-

TROL_0(RANGE) value.

For OUTPUT_CONTROL_0(RANGE) = 0

VMEAS=MUX_OUT

(2)

For OUTPUT_CONTROL_0(RANGE) = 1

VMEAS=MUX_OUT×2

(3)

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