Data Sheet

AD3530/AD3530R

REGISTER DETAILS

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Rev. 0 | 41 of 45

Table 33. Bit Descriptions for SW_LDAC_EN_0 (Continued)

Bits

Bit Name

Description

Reset

Access

0

SLD_EN_CH_0

Software LDAC Enable Channel 0. Enable/disable software LDAC functionality on Channel 0.

0x1

R/W

0: SLD En 0. Disable software LDAC on Channel 0.

1: SLD En 1. Enable software LDAC on Channel 0.

DAC REGISTER

Address: 0xD2 to 0xE0 (increments of 2), Reset: 0x0000, Name: DAC_CHn

16-bit data defines the voltage of VOUTn pin, where n is the channel number.

DAC_CH0: 0xD2-0xD3

DAC_CH1: 0xD4-0xD5

DAC_CH2: 0xD6-0xD7

DAC_CH3: 0xD8-0xD9

DAC_CH4: 0xDA-0xDB

DAC_CH5: 0xDC-0xDD

DAC_CH6: 0xDE-0xDF

DAC_CH7: 0xE0-0xE1

0

0

1

0

2

0

3

0

4

0

5

0

6

0

7

0

8

0

9

0

10

0

11

0

12

0

13

0

14

0

15

0

[15:0] DAC_VAL (R/W)

Table 34. Bit Descriptions for DAC_CHn

Bits

Bit Name

Description

Reset

Access

[15:0]

DAC_VAL

DAC Value. 16-bit data defines the voltage of the VOUTn pin, where n is the channel number.

0x0

R/W

MULTIPLE DAC REGISTER

Address: 0xE2, Reset: 0x0000, Name: MULTI_DAC_CH

Data written to this register also writes all DAC_CHn selected in MULTI_DAC_SEL_0.

0

0

1

0

2

0

3

0

4

0

5

0

6

0

7

0

8

0

9

0

10

0

11

0

12

0

13

0

14

0

15

0

[15:0] MULTI_DAC_VAL (R/W)

>

Table 35. Bit Descriptions for MULTI_DAC_CH

Bits

Bit Name

Description

Reset

Access

[15:0]

MULTI_DAC_VAL

Multiple DAC Value. Data written to all DAC_CHn selected in MULTI_DAC_SEL_0. Read data will always

return the latest data written.

0x0

R/W

MULTIPLE DAC SELECT 0 REGISTER

Address: 0xE4, Reset: 0xFF, Name: MULTI_DAC_SEL_0

Select which DAC_CHn will be written when a write operation is executed on MULTI_DAC_CH. Only applies DAC_CH0 to DAC_CH7.