Data Sheet

AD3530/AD3530R

REGISTER DETAILS

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Rev. 0 | 42 of 45

0

1

1

1

2

1

3

1

4

1

5

1

6

1

7

1

[7] MD_SEL_CH_7 (R/W)

[0] MD_SEL_CH_0 (R/W)

[6] MD_SEL_CH_6 (R/W)

[1] MD_SEL_CH_1 (R/W)

[5] MD_SEL_CH_5 (R/W)

[2] MD_SEL_CH_2 (R/W)

[4] MD_SEL_CH_4 (R/W)

[3] MD_SEL_CH_3 (R/W)

Table 36. Bit Descriptions for MULTI_DAC_SEL_0

Bits

Bit Name

Description

Reset

Access

7

MD_SEL_CH_7

Multiple DAC Select Channel 7. If selected, write operation on MULTI_DAC_CH also writes DAC_CH7 with the

same data. If deselected, write operation on MULTI_DAC_CH will have no effect on DAC_CH7.

0x1

R/W

0: MD Sel 0. Deselect DAC_CH7 for MULTI_DAC_CH operation.

1: MD Sel 1. Select DAC_CH7 for MULTI_DAC_CH operation.

6

MD_SEL_CH_6

Multiple DAC Select Channel 6. If selected, write operation on MULTI_DAC_CH also writes DAC_CH6 with the

same data. If deselected, write operation on MULTI_DAC_CH will have no effect on DAC_CH6.

0x1

R/W

0: MD Sel 0. Deselect DAC_CH6 for MULTI_DAC_CH operation.

1: MD Sel 1. Select DAC_CH6 for MULTI_DAC_CH operation.

5

MD_SEL_CH_5

Multiple DAC Select Channel 5. If selected, write operation on MULTI_DAC_CH also writes DAC_CH5 with the

same data. If deselected, write operation on MULTI_DAC_CH will have no effect on DAC_CH5.

0x1

R/W

0: MD Sel 0. Deselect DAC_CH5 for MULTI_DAC_CH operation.

1: MD Sel 1. Select DAC_CH5 for MULTI_DAC_CH operation.

4

MD_SEL_CH_4

Multiple DAC Select Channel 4. If selected, write operation on MULTI_DAC_CH also writes DAC_CH4 with the

same data. If deselected, write operation on MULTI_DAC_CH will have no effect on DAC_CH4.

0x1

R/W

0: MD Sel 0. Deselect DAC_CH4 for MULTI_DAC_CH operation.

1: MD Sel 1. Select DAC_CH4 for MULTI_DAC_CH operation.

3

MD_SEL_CH_3

Multiple DAC Select Channel 3. If selected, write operation on MULTI_DAC_CH also writes DAC_CH3 with the

same data. If deselected, write operation on MULTI_DAC_CH will have no effect on DAC_CH3.

0x1

R/W

0: MD Sel 0. Deselect DAC_CH3 for MULTI_DAC_CH operation.

1: MD Sel 1. Select DAC_CH3 for MULTI_DAC_CH operation.

2

MD_SEL_CH_2

Multiple DAC Select Channel 2. If selected, write operation on MULTI_DAC_CH also writes DAC_CH2 with the

same data. If deselected, write operation on MULTI_DAC_CH will have no effect on DAC_CH2.

0x1

R/W

0: MD Sel 0. Deselect DAC_CH2 for MULTI_DAC_CH operation.

1: MD Sel 1. Select DAC_CH2 for MULTI_DAC_CH operation.

1

MD_SEL_CH_1

Multiple DAC Select Channel 1. If selected, write operation on MULTI_DAC_CH also writes DAC_CH1 with the

same data. If deselected, write operation on MULTI_DAC_CH will have no effect on DAC_CH1.

0x1

R/W

0: MD Sel 0. Deselect DAC_CH1 for MULTI_DAC_CH operation.

1: MD Sel 1. Select DAC_CH1 for MULTI_DAC_CH operation.

0

MD_SEL_CH_0

Multiple DAC Select Channel 0. If selected, write operation on MULTI_DAC_CH also writes DAC_CH0 with the

same data. If deselected, write operation on MULTI_DAC_CH will have no effect on DAC_CH0.

0x1

R/W

0: MD Sel 0. Deselect DAC_CH0 for MULTI_DAC_CH operation.

1: MD Sel 1. Select DAC_CH0 for MULTI_DAC_CH operation.

SOFTWARE LDAC TRIGGER 0 REGISTER

Address: 0xE5, Reset: 0x00, Name: SW_LDAC_TRIG_A

Initiates transfer of INPUT_CHn to DAC_CHn. Only takes effect on enabled channels identified by SW_LDAC_EN_0.

0

0

1

0

2

0

3

0

4

0

5

0

6

0

7

0

[7] SLD_TRIG_A (W)

[6:0] RESERVED