AD3530R datasheet(24/45 Pages) AD

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Data Sheet

AD3530/AD3530R

THEORY OF OPERATION

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Rev. 0 | 24 of 45

be accessed in a single data phase before the byte address resets

to the one specified in the instruction phase.

The value of the STREAM_MODE(LOOP_COUNT) register can

be kept or returned to the default value of 0 when the frame

transaction is completed, that is, the CSB is brought high.

The STREAM_MODE register behavior is controlled by TRANS-

FER_CONFIG(KEEP_STREAM_LENTH_VAL).

Figure 66. Looping Enabled with LOOP_COUNT = 2

When using STREAM_MODE, be aware of the DAC update timings

mentioned in DAC Core Functions.

CRC ERROR DETECTION

The AD3530/AD3530R DACs feature optical cyclic redundancy

checks (CRCs) to provide error detection for SPI transactions

between the digital host and the DAC (target). The CRC error

detection is disabled by default. The CRC error detection allows

the SPI host and targets to detect bit transfer errors with significant

reliability. The CRC algorithm involves using a seed value and

polynomial division to generate a CRC code. The controller and

target both calculate the CRC code independently to determine the

validity of transferred data.

This DAC uses the CRC-8 standard with the following polynomial:

x 8 + x 2 + x + 1

(6)

CRC error detection is enabled with the CRC_EN and CRC_EN_B

bits in the INTERFACE_CONFIG_C register. The value of CRC_EN

is only updated if CRC_EN_B is set to the CRC_EN inverted value

in the same register write instruction. Therefore, to enable the CRC,

the CRC_EN must therefore be set to 0b01 while CRC_EN_B is set

to 0b10 in the same write transaction.

To disable the CRC, the CRC_EN must be set to 0b00 and the

CRC_EN_B is set to 0b11 in the same write transaction.

Writing inverted values to two separate fields reduces the chances

of CRC being enabled in error. The CSB must be brought high

at the end of the enable/disable write. The first CRC code must

be included after the register write/read data, immediately following

the register write transaction enabling the CRC. A register write

transaction that disables the CRC must still include the CRC code

on SDI, but the following transaction does not require the CRC

code.

Figure 67 and Figure 68 show how a CRC code is appended to the

write or read, respectively, for the digital host or DAC to validate

the data. For register writes, the digital host must generate the CRC

using the calculation described in Equation 6. For register reads,

the host must also send the correct CRC byte that is checked

by the DAC. The first byte of data sent contributes to the CRC

calculation. Therefore, a value of 0x00 is recommended. In the

same read transaction, the DAC provides the CRC code for the

digital host to verify.

When accessing multibyte registers with the CRC error detection

enabled, the CRC code is placed after all bytes of register data.

When the CRC error detection is enabled, the DAC does not up-

date its register contents in response to a register write transaction

unless it receives a valid CRC code at the end of the register data

on the SDI. If the CRC code is invalid, or the digital host fails

to transmit the CRC code, the AD3530/AD3530R do not update

the register contents, and the CRC_ERR flag in the INTERFACE_

STATUS_A register is set. The CRC_ERR flag is write-1-to-clear

(W1C) and the correct CRC is required for the write to clear to take

effect.

Table 14 shows the seed value used in the CRC code calculation

and how it is transmitted for both single instruction mode and

streaming mode. When using single instruction mode, every CRC

code in a SPI frame uses 0xA5 as the seed value to prevent stuck

at fault conditions for Address 0x0000.

When using the streaming mode, the first CRC code in a SPI frame

also uses 0xA5 as the seed value, but subsequent CRC codes

in the same frame are calculated using the LSB of the register

address being accessed in the SPI transaction as the seed value.

Figure 67. SPI Write with CRC Enabled

Figure 68. SPI Read with CRC Enabled

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