AD3530R datasheet(22/45 Pages) AD

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Data Sheet

AD3530/AD3530R

THEORY OF OPERATION

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Rev. 0 | 22 of 45

Hardware Reset

RESETB is an active low signal that is falling edge sensitive. As-

serting RESETB sets the device into the POR state. While RESETB

is asserted, all SPI transactions and LDACB pulses are ignored,

and the SDO output is in a high-Z state.

When RESETB is deasserted, the digital core initialization is per-

formed and all DAC registers are reset to their default values. The

digital core must finish the initialization procedure for around 150ns

before any SPI transactions are performed.

Software Reset

The device can also be reset using the serial interface by setting

the SW_RESET bit and RESET_SW bit in the INTERFACE_CON-

FIG_A register. Both bit fields must be written at the same data

phase to trigger a successful software reset. After the software

reset transaction, the POR sequence and digital core initialization

are performed, and all DAC registers are reset to the default val-

ues except for the INTERFACE_CONFIG_A register. Succeeding

SPI transactions cannot be started until after around 150ns have

passed after the last SCLK on the soft reset transaction. See the

Timing Characteristics section for additional information.

SERIAL INTERFACE

The AD3530/AD3530R use 4-wire serial interfaces (CSB, SCLK,

SDI, and SDO) that are compatible with classic SPI, QSPI, and

MICROWIRE interface standards, as well as most digital signal

processors (DSPs). See Figure 2 for a timing diagram of a typical

write sequence. Data is sampled by the AD3530/AD3530R on the

positive edge of the clock. This corresponds to either SPI Mode 0 or

Mode 3.

The 15-bit addressing is enabled by default and, by configuring

the SHORT_INSTRUCTION bit on the Interface Configuration B

below 0x80.

Figure 60. Classic SPI Write

Figure 61. Classic SPI Read

SPI Frame Synchronization

The CSB pin frames data during a SPI transaction. A falling edge

on the CSB enables the digital interface and initiates an SPI trans-

action. Each SPI transaction consists of at least one instruction

phase and one data phase. For all SPI transactions, data is aligned

MSB first. Deasserting the CSB during a SPI transaction terminates

part or all of the data transfer and disables the digital interface. If

the CSB is deasserted (returned high) after one or more registers

are written, completed registers are written or read, but any partially

written register is aborted. Figure 60 and Figure 61 show detailed

timing diagrams for performing register reads and writes via the SPI

interface.

Instruction Phase

Every SPI frame starts with the instruction phase. The instruction

phase immediately follows the falling edge of the CSB that initiates

the SPI transaction. The instruction phase consists of a read/write

bit (R/W) followed by a register address word. Setting R/W low

initiates a write instruction, whereas setting R/W high initiates a

read instruction. The register address word specifies the address

of the register to be accessed. The register address word is 15-bit

in length by default. If required, enable 7-bit addressing with the

SHORT_INSTRUCTION bit on INTERFACE_CONFIG_B register.

See the Interface Configuration B Register section for additional

information.

Data Phase

The data phase immediately follows the instruction phase (as

shown in Figure 62 and Figure 63. The data phase can include

the data for a single-byte register, a multibyte register, or multiple

registers.

If the data phase of a SPI write transaction does not include

the entire byte of data for the register being updated, the

contents of the register are not updated, and INTERFACE_STA-

TUS_A(CLOCK_COUNT_ERR) is set.

Multibyte Registers

Besides the 1-byte registers, the AD3530/AD3530R also contain

registers with two bytes of data stored in adjacent addresses

that are referred to as multibyte registers. When writing to a multi-

byte register, all bytes must be accessed in a single SPI transac-

tion. For this reason, the INTERFACE_CONFIG_C(STRICT_REG-

ISTER_ACCESS) is read only and set to 1. A write transaction to a

multibyte register takes effect after the 16th SCLK edge of the data

phase.

The address of a multibyte register always depends on IN-

TERFACE_CONFIG_A(ADDR_ASCENSTION). With addresses de-

scending, the first byte accessed in the data phase must be the

most significant byte of the multibyte register, and each subsequent

byte corresponds to the data in the next lowest address. With

addresses ascending, the first byte accessed in the data phase

must be the least significant byte of the multibyte register, and

each subsequent byte corresponds to the data in the next highest

address.

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