AD3530R datasheet(23/45 Pages) AD

23 / 45 page

Data Sheet

AD3530/AD3530R

THEORY OF OPERATION

analog.com

Rev. 0 | 23 of 45

For example, the DAC_CH0 register is two bytes long, and the

addresses of its least significant byte and most significant byte are

0xD2 and 0xD3, respectively. Figure 62 and Figure 63 show read

transactions of this register for address ascending and descending

mode, respectively.

Address direction is selected with INTERFACE_CON-

FIG_A(ADDR_ASCENSION). If this bit is set to 0, the address

decrements after each byte is accessed. If this bit is set to 1,

the address increments after each byte is accessed. If a SPI

write transaction to a multibyte register is attempted on a per byte

basis, the register contents are not updated on the device, and

INTERFACE_STATUS_A(REGISTER_PARTIAL_ACCESS_ERR) is

set.

This device contains the following multibyte registers: DAC_CHn,

Input_CHn, MULTI_DAC_CH, and MULTI_INPUT_CH.

Figure 62. Multibyte Read in Ascending Mode

Figure 63. Multibyte Read in Descending Mode

Single Instruction Mode

When INTERFACE_CONFIG_B(SINGLE_INST) is set to 1, stream-

ing mode is disabled, and single instruction mode is enabled. In

single instruction mode, the data phase consists of data for a

single register, and each data phase must be followed by a new

instruction phase (even if CSB remains low). Single instruction

mode allows the digital host to quickly read from and write to

registers with nonadjacent addresses in a single SPI frame (see

Figure 64), whereas streaming mode only allows either reading or

writing to contiguous registers without pulsing CSB high to initiate a

new instruction phase.

Figure 64. Single Instruction Mode

When accessing multibyte registers in single instruction mode,

data phase should include all 2 bytes or 16 SCLK cycles, and

the register address order is dependent on INTERFACE_CON-

FIG_A(ADDR_ASCENSION).

Streaming Mode

When the INTERFACE_CONFIG_B(SINGLE_INST) bit is set to 0,

single instruction mode is disabled, and streaming mode is enabled.

In streaming mode, multiple registers with adjacent addresses can

be accessed with a single instruction phase and data phase, allow-

ing efficient access of contiguous regions of memory (for example,

during initial device configuration). The streaming mode is selected

by default.

When in streaming mode, each SPI frame consists of a single in-

struction phase and the following data phase contains data for mul-

tiple registers with adjacent addresses. A starting register address

is specified by the digital host in the instruction phase, and this

address is automatically incremented or decremented (based on

the address direction setting) after each byte of data is accessed.

Therefore, the data phase can be multiple bytes long, and each

consecutive byte of read or write data corresponds to the next

highest or lowest register address (for ascending and descending

address direction, respectively).

When writing to a multibyte register in streaming mode with address

ascending, the LSB of the register must be addressed in the

instruction phase and data must be provided starting from the LSB

in the data phase. When writing to a multibyte register in streaming

mode with the address descending, the user must start addressing

the most significant byte of the register in the instruction phase

and provide data starting from the most significant byte in the data

phase.

When reading from a multibyte register in streaming mode with

address descending, read back the data starting from the MSB.

When reading from a multibyte register in streaming mode with

address ascending, read back data starting from the LSB.

Figure 65. Streaming Mode SPI transfer

The STREAM_MODE register can be used to specify a set of

consecutive registers to loop through in the data phase. Looping

allows the digital host to repeatedly read from or write to a set of

registers as efficiently as possible.

If the address direction is set to descending, the address decre-

ments until it reaches Address 0x00. On the subsequent byte

access, the address is set to the highest valued byte address

available (0xF9).

If address direction is set to ascending, the address increments

until it reaches the highest valued byte address available (0xF9).

On the subsequent byte access, the address is reset to 0x00.

If STREAM_MODE is set to a value other than 0, looping is ena-

bled, and the value in STREAM_MODE sets the number of bytes to

AD3530R 数据表(PDF) 23 Page - Analog Devices

AD3530R 数据表(HTML) 23 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

数据表下载