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KSZ9567R 数据表(PDF) 183 Page - Microchip Technology |
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KSZ9567R 数据表(HTML) 183 Page - Microchip Technology |
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183 / 233 page  2022 Microchip Technology Inc. and its subsidiaries DS00002329E-page 183 KSZ9567R 5.2.11 PORT N: PORT SWITCH PTP CONTROL REGISTERS (0xNC00 - 0xNCFF) 5.2.11.1 Port PTP Receive Latency Register 5.2.11.2 Port PTP Transmit Latency Register 5.2.11.3 Port PTP Asymmetry Correction Register Address: 0xNC00 - 0xNC01 Port N: 1-7 Size: 16 bits Bits Description Type Default 15:0 PTP Port N RX Latency in Nanoseconds (PTP_RX_LATENCY[15:0]) This field is used to set the fixed receive delay value from the port N wire to the RX timestamp reference point. The default value is 415ns. R/W 0x019F Address: 0xNC02 - 0xNC03 Port N: 1-7 Size: 16 bits Bits Description Type Default 15:0 PTP Port N TX Latency in Nanoseconds (PTP_TX_LATENCY[15:0]) This field is used to set the fixed transmit delay value from the port N TX time- stamp to the wire. The default value is 45ns. R/W 0x002D Address: 0xNC04 - 0xNC05 Port N: 1-7 Size: 16 bits Bits Description Type Default 15 PTP Port N Asymmetry Correction Sign Bit (PTP_ASYM_COR_SIGN) 1 = The magnitude in the PTP_ASM_COR field of this register is negative. 0 = The magnitude in the PTP_ASM_COR field of this register is positive. R/W 0b 14:0 PTP Port N Asymmetry Correction in Nanoseconds (PTP_ASYM_COR) This field is used to set the fixed asymmetry value to add in the correction field for ingress Sync and Pdelay_Resp or to subtract from the correction field for egress Delay_Req and Pdelay_Req. R/W 0x0000 |
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