KSZ9567R_V01 datasheet(76/233 Pages) MICROCHIP

76 / 233 page

KSZ9567R

DS00002329E-page 76

 2022 Microchip Technology Inc. and its subsidiaries

5.1.2.3

In-Band Management (IBA) Control Register

This register controls the In-Band Access (IBA) feature.

4:2

SYNCLKO Source

000 = From crystal / clock input at XI pin

001 = From port 1 recovered clock

010 = From port 2 recovered clock

011 = From port 3 recovered clock

100 = From port 4 recovered clock

101 = From port 5 recovered clock

110 – 111 = Reserved

R/W

000b

SYNCLKO Output Pin Enable

0 = Disabled

1 = Enabled

R/W

SYNCLKO Frequency

0 = 25 MHz

1 = 125 MHz

R/W

Address:

0x0104 - 0x0107

Size:

32 bits

Bits

Description

Type

Default

IBA Enable

The initial value is strapped in from the RX_DV7/CRS_DV7/RX_CTL7 pin.

0 = Disabled

1 = Enabled

Note:

If using I2C, do not enable IBA.

R/W

Note 5-1

IBA Destination MAC Address Match Enable

Set this bit to enable checking of the destination MAC address in received

IBA frames against the switch MAC address in the Switch MAC Address 0

discarded.

When not enabled, the MAC address is not checked.

R/W

IBA Reset

Set this bit to initialize the IBA state machine. This bit is self-clearing.

R/W

28:24

RESERVED

0x00

23:22

Priority Queue for IBA response

Specifies the transmit priority queue for the IBA response frame. Typically

this value is not changed.

R/W

01b

21:19

RESERVED

00_0b

Bits

Description

Type

Default

KSZ9567R 数据表(PDF) 76 Page - Microchip Technology

KSZ9567R 数据表(HTML) 76 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载