KSZ9567R_V01 datasheet(62/233 Pages) MICROCHIP

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KSZ9567R

DS00002329E-page 62

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4.13

MAC Interface (RGMII/MII/RMII Port 6-7)

Strapping options are used to individually select any of these MAC interface options for ports 6 and 7:

• Media Independent Interface (MII): Supports 100 and 10 Mbps data rates

• Reduced Media Independent Interface (RMII): Supports 100 and 10 Mbps data rates

• Reduced Gigabit Media Independent Interface (RGMII): Supports 1000, 100 and 10 Mbps data rates

Note that the signals on the KSZ9567R MAC interfaces are named as they would be for a PHY: the TX direction is into

the KSZ9567R, while the RX direction is out of the KSZ9567R, as if to a host processor with integrated MAC. Signal

connection to such a “MAC” device is TX-to-TX, and RX-to-RX.

An external PHY (such as the Microchip KSZ9031RNX) may be connected to either port, but in that case the signal

connection will be RX-to-TX, and TX-to-RX.

The RGMII/MII/RMII interfaces are powered by the VDDIO power supply.

FIGURE 4-17:

IN-BAND MANAGEMENT FRAME FORMAT

LSB

MSB

PREAMBLE

SFD

7 Bytes

1 Byte

DES. ADDRESS

6 Bytes

IBAF TAG TYPE

2 Bytes

SRC. ADDRESS

6 Bytes

IBAF TAG CONTROL INFO.

2 Bytes

46 bit address

i/g

u/l

i/g=0, Individual Address; i/g=1, Group Address

u/l=0, Globally Admin. Addr. u/l=1, Locally Admin. Addr.

2 Bytes

MAC LENGTH/TYPE

2 Bytes

TPID

10011000

00000000

0x9800 for 98xx Family

Reserved

010xxxxx

11111110

Sequence #

cfi

3 bits of Priority, 1 bit of Canonical Format Indicator = 0

4 bits of mode, 8 bits of sequence #

IBAF TAG

2 Bytes

ACCESS COMMAND

4 Bytes

DATA

4 Bytes

ACCESS CODE

4 Bytes

EXTENSION

Variable

FRAME CHECK SEQUENCE

4 Bytes

PAD

Variable

IBAF

Layer 3

Data

–

MAC

DATA

0eeeeAAAAAAAA

OP.

Code

Bits Transmitted from Left to Right

mode

ACCESS FORMAT

Reserved

0x0001 = Rd/Wr,

0x0002 = Burst

ACCESS COMMAND/DATA

DATA

AAAAAAAAAAAAAAAA

COMMAND = 0x0001 (Rd/Wr)

0000000000000

OP.

Code

00000000000aaaaa

COMMAND = 0x0002 (Dump)

0xdddddddd

COMMAND = 0x0001 (Rd/Wr)

3 bits of OP code:

001 = READ, 010 = WRITE,

100 = WAIT on 0, 101 = WAIT on 1,

110 = MODIFY to 0, 111 = MODIFY to 1,

000 = end of command list

eeee = Byte enable

AAAA..AAAA[23:0] = Register Address

000000AAAAAAAA

Dir

AAAAAAAAAAAAAAAA

COMMAND = 0x0002 (Burst)

2 bits of Direction:

01 = READ, 10 = WRITE,

AAAA..AAAA[23:0] = Starting Register Address

0xmaskmask

COMMAND = 0x0001 (WAIT/

MODIFY)

Mask (1) = bit in reg. to be tested for OP code 100/101

set (1) = bit to be set to 0/1 based on OP code 110/111

dddddddd = data written/read

26 0's and 6 bits of burst count

COMMAND = 0x0002 (Burst)

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