KSZ9567R_V01 datasheet(205/233 Pages) MICROCHIP

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DS00002329E-page 205

KSZ9567R

6.4

Timing Specifications

This section details the various timing specifications of the device.

6.4.1

RGMII TIMING

Figure 6-1 illustrates the RGMII timing requirements.

Note 6-5

For cases where there is no (or insufficient) skew between the input data and input clock, it is

possible to add internal delay to the TX_CLK pinout by setting the RGMII Ingress Internal Delay bit

in the XMII Port Control 1 Register register. This feature reduces the setup time requirement and

increases the hold time requirement nominally by 1.3ns.

Note 6-6

The RGMII interface adheres to the RGMII Specification Version 2.0, which specified that the driving

device delay the output clock relative to the output data. This is the TSKEW parameter. This skew can

be disabled by clearing the RGMII Egress Internal Delay bit in the XMII Port Control 1 Register

Note:

The I2C interface timing adheres to the NXP I2C-Bus Specification (UM10204, Rev. 6) (high-speed mode

and slower). Refer to the I2C-Bus Specification for additional information.

FIGURE 6-1:

RGMII TIMING

TABLE 6-2:

RGMII TIMING VALUES

Symbol

Description

Min

Typ

Max

Units

TSETUP

Port 6 Data to clock input setup (Note 6-5)2.2

Port 7 Data to clock input setup (Note 6-5)1.3

THOLD

Port 6 Data to clock input hold (Note 6-5)0

Port 7 Data to clock input hold (Note 6-5)0.7

TSKEW

Data to clock output skew (Note 6-6)1.1

2.0

TCYC

Clock cycle duration (Note 6-7)

7.288.8

Duty_G

1000Mbps duty cycle

Duty_T

10/100Mbps duty cycle

Tr / Tf

Rise / Fall time (20-80%)

Note 6-8

TX_CLK

TX_CTL

TXD[3:0]

TCYC

TSETUP

THOLD

TSETUP

THOLD

RX_CTL

RXD[3:0]

RX_CLK

TSKEW

TCYC

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