KSZ9567R_V01 datasheet(228/233 Pages) MICROCHIP

228 / 233 page

KSZ9567R

DS00002329E-page 228

 2022 Microchip Technology Inc. and its subsidiaries

Section 5.2.7.4, "Port

Authentication Control Reg-

ister," on page 172

Corrected bits 1:0 description.

Section 5.1.6.11, "Global

PTP Message Config 1 Reg-

ister," on page 116

Corrected 802.3AS to 802.1AS and added descrip-

tions.

Section 5.2.2.16, "PHY

LinkMD Register," on

page 151

Updated register bit descriptions.

Section 5.1.1.4, "Global

Chip ID 3 Register," on

page 70

Corrected bit 0 description.

Section 5.4, "MDIO Manage-

able Device (MMD) Regis-

ters (Indirect)," on page 199

Corrected the MMD register read example.

Table 6-2, "RGMII Timing

Values"

Revised minimum RGMII TSKEW parameter.

Table 3-3, "Configuration

Strap Descriptions"

Corrected swapping of LED2_0 and LED4_0,

added notes in strapping. Corrected RXD6_0 and

RXD7_0 in strapping table.

DS00002329B (03-10-17)

Section 4.1.10, "Remote

PHY Loopback," on page 24

Added new section.

Section 4.4.5.1, "Two Rate

Three Color Marker," on

page 37

Added new section.

Section 4.4.5.2, "Weighted

Random Early Detection

(WRED)," on page 37

Updated section with additional information.

Section 4.11.3, "MII Man-

agement (MIIM) Interface,"

on page 59, Section

4.11.3.1, "Standard MIIM

Registers (Direct)", Section

4.11.3.2, "MDIO Manage-

able Device (MMD) Regis-

ters (Indirect)"

Added additional information to end of section.

Added new subsections on Standard MIIM and

MMD registers.

Section 5.4, "MDIO Manage-

able Device (MMD) Regis-

ters (Indirect)," on page 199

Added new section.

Section 5.2.7.8, "Port Police

Queue Rate Register," on

page 174 through Section

5.2.7.14, "Port WRED

Queue Performance Moni-

tor Control Register," on

page 176

Added new register definitions.

TABLE A-1:

REVISION HISTORY (CONTINUED)

Revision

Section/Figure/Entry

Correction

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