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KSZ9567R 数据表(PDF) 106 Page - Microchip Technology |
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KSZ9567R 数据表(HTML) 106 Page - Microchip Technology |
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106 / 233 page  KSZ9567R DS00002329E-page 106 2022 Microchip Technology Inc. and its subsidiaries 5.1.4.71 Queue Management Control 0 Register 5.1.4.72 Global PM Available Register Address: 0x0390 - 0x0393 Size: 32 bits Bits Description Type Default 31:8 RESERVED RO 0x000000 7:6 Priority_2Q When the 2 queue configuration is selected, this determines how to map the 2-bit priority regeneration result from the Port Priority to Queue Mapping Register into 2 queues. 00 = Priorities 0, 1, 2 map to the Low priority queue. Priority 3 maps to the High priority queue. 01 = Not used. 10 = Priorities 0, 1 map to the Low priority queue. Priorities 2, 3 map to the High priority queue. 11 = Priority 0 maps to the Low priority queue. Priorities 1, 2, 3 map to the High priority queue. R/W 10b 5:2 RESERVED R/W 00_00b 1 Unicast Port VLAN Membership Discard This bit applies to the Port VLAN Membership function in registers 0xNA04- 07. 1 = All frames are restricted to the forwarding ports as defined in the Port Control 1 Register. 0 = Frames forwarding to a single destination port are not limited to the forwarding ports defined in the Port Control 1 Register. Note that when mirroring is enabled, a single-destination frames will be dropped if it is mirrored to another port. R/W 1b 0 RESERVED R/W 0b Address: 0x03AC - 0x03AF Size: 32 bits Bits Description Type Default 31:27 RESERVED RO 0x00 26:16 Packet Memory Available Block Count (PMAVBC) In real-time, the number of blocks available (unused) in the switch packet memory. The default value is the max value, when there are no packets in the switch. RO 0x7E8 15:0 RESERVED RO 0b |
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