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KSZ9567R 数据表(PDF) 55 Page - Microchip Technology |
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KSZ9567R 数据表(HTML) 55 Page - Microchip Technology |
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55 / 233 page  2022 Microchip Technology Inc. and its subsidiaries DS00002329E-page 55 KSZ9567R 4.9 Power The KSZ9567R requires two to three supply voltages. The device core operates from a 1.2V supply (DVDDL and AVDDL). The PHY transceivers and XI/XO crystal/clock interface operate from a 2.5V supply (AVDDH). The digital I/ O's can be operated from 1.8V, 2.5V or 3.3V (VDDIO). The digital I/Os powered from VDDIO include RGMII, RMII, MII, SPI, I2C, MIIM, LED, RESET_N, PME_N, INTRP_N and SYNCLKO. An example power connection diagram can be seen in Figure 4-10 . 4.10 Power Management The device supports enhanced power management features in a low-power state with energy detection to ensure low- power dissipation during device idle periods. There are three operation modes under the power management function which are implemented globally (i.e., applying to all ports): • Normal Operation Mode • Energy Detect Mode • Global Soft Power Down Mode Table 4-24 summarizes all internal function blocks status under the three power-management operation modes. FIGURE 4-10: POWER CONNECTION DIAGRAM 0.1µF 22µF 0.1µF VDDIO VDDIO VDDIO AVDDH AVDDH AVDDH AVDDH AVDDH AVDDH AVDDH DVDDL AVDDL AVDDL AVDDL AVDDL AVDDL AVDDL AVDDL AVDDL AVDDL DVDDL DVDDL DVDDL DVDDL DVDDL DVDDL DVDDL GND GND GND GND GND GND GND (exposed pad) +1.8V, 2.5V or 3.3V +2.5V +1.2V 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 22µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 22µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 10µF |
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