KSZ9567R datasheet(75/233 Pages) MICROCHIP

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DS00002329E-page 75

KSZ9567R

5.1.2

GLOBAL I/O CONTROL REGISTERS (0x0100 - 0x01FF)

5.1.2.1

Serial I/O Control Register

5.1.2.2

Output Clock Control Register

Address:

0x0100

Size:

8 bits

Bits

Description

Type

Default

7:3

RESERVED

R/W

0100_0b

MIIM Preamble Suppression

This feature affects only the MIIM (MDIO / MDC) interface. When using SPI

or I2C, this bit has no effect.

0 = Normal operation. The switch always expects the MIIM preamble.

1 = The switch will respond to MIIM commands even in the absence of a

preamble.

R/W

Automatic SPI Data Out Edge Select

When enabled, this feature automatically determines the edge of SCL that is

used to clock out the SPI data on SDO. If SCL ≥ ~25MHz, SDO data is

clocked by the rising edge of SCL. If SCL < ~25 MHz, SDO data is clocked

by the falling edge of SCL.

0 = The automatic feature is disabled, and bit 0 determines the SCL clock

edge used for SDO.

1 = The automatic feature is enabled, and bit 0 is ignored.

R/W

SPI Data Out Edge Select

When bit 1 is zero, then this bit determines the clock edge used for SPI data

out. When bit 1 is set to 1, this bit is ignored.

0 = SDO data is clocked by the falling edge of SCL

1 = SDO data is clocked by the rising edge of SCL

R/W

Address:

0x0103

Size:

8 bits

Bits

Description

Type

Default

Recovered Clock Ready (REC_CLK_RDY)

0 = The selected recovered clock is not ready

1 = The selected recovered clock is ready

6:5

RESERVED

00b

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