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KSZ9567R 数据表(PDF) 172 Page - Microchip Technology |
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KSZ9567R 数据表(HTML) 172 Page - Microchip Technology |
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172 / 233 page  KSZ9567R DS00002329E-page 172 2022 Microchip Technology Inc. and its subsidiaries 5.2.7.4 Port Authentication Control Register 5.2.7.5 Port Pointer Register 4 Discard Untagged Packets This bit should be left as 0 for the host port. 1 = Any ingress packet at this port without an IEEE 802.1Q tag is discarded. 0 = Do not discard. R/W 0b 3 Discard Tagged Packets 1 = Any ingress packet at this port with an IEEE 802.1Q tag is discarded. 0 = Do not discard. R/W 0b 2:0 Port Default Priority Classification If Diffserv classification, 802.1p classification and VLAN classification are not enabled or fail to classify, ingress packets at this port will be classified with the priority specified here. Possible values are 0 to 7. R/W 000b Address: 0xN803 Port N: 1-7 Size: 8 bits Bits Description Type Default 7:3 RESERVED RO 0000_0b 2 Access Control List (ACL) Enable 1 = enable 0 = disable R/O 0b 1:0 Authentication Mode 00 = Reserved 01 = Block Mode. Authentication is enabled. When ACL is enabled, all traffic that misses the ACL rules is blocked; otherwise ACL actions apply. 10 = Pass Mode. Authentication is disabled. When ACL is enabled, all traffic that misses the ACL rules is forwarded; otherwise ACL actions apply. 11 = Trap Mode. Authentication is enabled. All traffic is forwarded to the host port. When ACL is enabled, all traffic that misses the ACL rules is blocked; otherwise ACL actions apply. R/W 00b Address: 0xN804 - 0xN807 Port N: 1-7 Size: 32 bits Bits Description Type Default 31:19 RESERVED RO 0x0000 18:16 Port Index Used to point to the indirect mapping locations for the 7 ports R/W 000b 15:2 RESERVED RO 0x0000 Bits Description Type Default |
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