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STA538B 数据表(PDF) 16 Page - STMicroelectronics |
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STA538B 数据表(HTML) 16 Page - STMicroelectronics |
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16 / 59 page ![]() Digital processing STA538 16/59 4 Digital processing The STA538 processor block is a digital block providing two channels of audio processing and channel-mapping capability. 4.1 Signal processing flow I2S or stereo ADC data can be selected. The I2S frequency range is from 8 kHz to 192 kHz. ADC sampling frequency can be selected from 8 kHz to 48 kHz. 4.2 I2C interface disabled When pin I2CDIS = 1, the SDA, SCL, LRCLKO and BICLKO pins can be pulled high or low to change certain parameters of operation. ● SDA = 0: FFX input comes from ADC SDA = 1: FFX input comes from digital audio interface ● SCL = 0: binary output mode (binary soft start/stop enabled) SCL = 1: phase shift output mode ● LRCLKO = 0: no volume change LRCLKO = 1: volume up ● BICLKO = 0: no volume change BICLKO = 1: volume down At power up, the master volume is set to -60 dB. When holding pin LRCLKO = 1 and pin BICLKO = 1 simultaneously, the master volume is set to 0 dB. A high pulse on pin LRCLKO causes a master volume change of +0.5 dB and a high pulse on pin BICLKO causes a master volume change of -0.5 dB. |
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