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STA538B 数据表(PDF) 45 Page - STMicroelectronics |
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STA538B 数据表(HTML) 45 Page - STMicroelectronics |
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45 / 59 page  STA538 Registers 45/59 P2SCFG1 Parallel-to-serial audio interface configuration register 1 Address: 0x0D Type: R/W Buffer: No Reset: 0x91 Description: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PDATA_LENGTH[1:0] BICLK_OS[1:0] MAP_L[1:0] MAP_R[1:0] 7:6 PDATA_LENGTH[1:0]: serial-to-parallel interface data length: 10: default Length is (PDATA_LENGTH+1) * 8 bit Default is 24 bits 5:4 BICLK_OS[1:0]: bit clock oversampling: 01: default Value is (BICLK_OS+1) * 32 fs Default is 64 fs 3:2 MAP_L[1:0]: left data-mapping slot: 00: default Value is nth slot Default is slot0 1:0 MAP_R[1:0]: right channel data-mapping slot: 01: default Value is nth slot Default is slot1 |
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