STA538B datasheet(44/59 Pages) STMICROELECTRONICS

部件名	STA538B

功能描述	2 x 1.3 W class-D amplifier with analog or digital input 2.0 multichannel digital audio processor with FFX

PDF	59 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

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44 / 59 page

Registers

STA538

44/59

P2SCFG0

Parallel-to-serial audio interface configuration

Address:

0x0C

Type:

R/W

Buffer:

Reset:

0xD3

Description:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BICLK_ STRB

LRCLK_LEFT

SDATAO_ACT

MSB_FIRST

DATA_FORMAT[2:0]

MASTER_

MODE

7 BICLK_STRB: defines the bit clock edges:

0: strobe is falling edge, active edge is rising

1: strobe is rising edge, active edge is falling (default)

6 LRCLK_LEFT: defines the channel for the LR clock:

0: clock is low for left channel, high for right channel

1: clock is high for left channel, low for right channel (default)

5 SDATAO_ ACT: sets the behavior of pin SDATAO:

0: output is tri-stated when no data is sent (default)

1: output is never in tri-state (it is 0 when no data is sent)

4 MSB_FIRST: data alignment in the protocol for SDATAI and SDATAO:

0: LSB is the first bit

1: MSB is the first bit (default)

3:1 DATA_FORMAT[2:0]: serial interface protocol format:

000: left justified

001: I2S (default)

010: right justified

100: PCM no delay

101: PCM delay

111: DSP

0 MASTER_ MODE: selects serial interface master/slave mode:

0: slave

1: master (default)

STA538B 数据表(PDF) 44 Page - STMicroelectronics

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