STV7622

Circuit description

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5

Circuit description

The STV7622 includes all the logic and power circuits necessary to drive the column

electrodes of a Plasma Display Panel (PDP). A low-voltage logic block manages data

information, and a high-voltage block converts the low-voltage information stored in the logic

block into high-voltage signals applied to the display electrodes.

5.1

Data input block

The Data Bus is TTL- and LVCMOS-compatible and can also operate in an RSDS (Reduced

Swing Differential Signaling) mode. The maximum clock frequency is 60 MHz.

The data input block consists of several shift registers operating in parallel to load the binary

values of the digital video. The number of cells in each shift register is defined by the BS pin

as described below in Table 2.

For the 3

× 64 bit configuration, only pins DB1, DB2 and DB3 of the input data bus are used,

while for the 6

× 32 and 2 × 3 × 32 bit configurations all 6 bits of the input data bus input,

pins DB1 to DB6, are used.

The DIR input pin is used to select the shift register loading direction.

Data is shifted for each low-to-high transition of the clock signal (CLK1). The maximum

frequency of the clock is 60MHz, which is equivalent to a 360MHz serial shift register for a

6

× 32-bit arrangement.

When the /STB signal goes from high-to-low, data is transferred from the shift register to the

latch and to the power output stages. All output data is stored and held in the latch stage

when the latch input is pulled back High.

The core of the STV7622 is powered by 5V. All logic inputs can be driven either by 5V or

3.3V CMOS logic.

The tables in the following sections describe the position of the first data sampled by the first

rising edge of the CLK1 clock.

Table 2.

BS1/BS2 truth table

BS1

BS2

Shift register configuration

L

L

6

× 32 bits

H

L

3

× 64 bits

L

H

RSDS mode

H

H

2

× 3 × 32 bits (96 + 96)