Circuit description

STV7622

8/32

5.2

3 x 64-bit data bus, standard transmission (BS1 = H, BS2 = L)

The data bus is in 3-bit mode (DB1 to DB3 active) for BS1 = H and BS2 = L.

Data on DB1 is sampled by the first clock pulse and shifted from position 1 to position 190

after 64 clock pulses. The data is then applied to output 190, on the high-to-low transition of

/STB.

5.3

6 x 32-bit data bus, standard transmission (BS1 = L, BS2 = L)

The data bus is in 6-bit mode (DB1 to DB6 active) for BS1 = L and BS2 = L.

Table 4 below describes how data is shifted in the register.

Table 3.

3 x 64-bit data bus transmission

BS1

BS2

DIR

Input

Clock pulse number

Comment

Position

01

02

03

…

62

63

64

H

L

L

DB1

DB2

DB3

OUT

OUT

OUT

01

02

03

04

05

06

07

08

09

184

185

186

187

188

189

190

191

192

Left/Right

shift

H

L

H

DB1

DB2

DB3

OUT

OUT

OUT

190

191

192

187

188

189

184

185

186

07

08

09

04

05

06

01

02

03

Right/Left

shift

Table 4.

6 x 32-bit data bus transmission

BS1

BS2

DIR

Input

Position

01

02

03

…

30

31

32

Comment

Clock pulse number

L

L

L

DB1

DB2

DB3

DB4

DB5

DB6

OUT

OUT

OUT

OUT

OUT

OUT

01

02

03

04

05

06

07

08

09

10

11

12

13

14

15

16

17

18

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

Left/Right

shift

L

L

H

DB1

DB2

DB3

DB4

DB5

DB6

OUT

OUT

OUT

OUT

OUT

OUT

187

188

189

190

191

192

181

182

183

184

185

186

175

176

177

178

179

180

13

14

15

16

17

18

07

08

09

10

11

12

01

02

03

04

05

06

Right/Left

shift