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ADIN1111CCPZ-R7 数据表(PDF) 63 Page - Analog Devices |
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ADIN1111CCPZ-R7 数据表(HTML) 63 Page - Analog Devices |
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63 / 109 page  Data Sheet ADIN1111 REGISTERS analog.com Rev. A | 63 of 109 Time Stamp Accumulator Addend Register Address: 0x80, Reset: 0x85555555, Name: TS_ADDEND Table 81. Bit Descriptions for TS_ADDEND Bits Bit Name Description Reset Access [31:0] TS_ADDEND Time Stamp Accumulator Addend. 0x85555555 R/W Timer Update Compare Register Address: 0x81, Reset: 0x3B9ACA00, Name: TS_1SEC_CMP Table 82. Bit Descriptions for TS_1SEC_CMP Bits Bit Name Description Reset Access [31:0] TS_1SEC_CMP Time Stamp 1 Second Compare Value. 0x3B9ACA00 R/W Seconds Counter Register Address: 0x82, Reset: 0x00000000, Name: TS_SEC_CNT Use this register to write to the seconds counter. Table 83. Bit Descriptions for TS_SEC_CNT Bits Bit Name Description Reset Access [31:0] TS_SEC_CNT Write to the Seconds Counter. 0x0 R/W Nanoseconds Counter Register Address: 0x83, Reset: 0x00000000, Name: TS_NS_CNT Use this register to write to the nanoseconds counter. Table 84. Bit Descriptions for TS_NS_CNT Bits Bit Name Description Reset Access [31:0] TS_NS_CNT Write to the Nanoseconds Counter. This register must be programmed with a value that is divisible by 16 decimal because the counters are driven by a 120 MHz clock and increment in steps of 16. 0x0 R/W Timer Configuration Register Address: 0x84, Reset: 0x00000000, Name: TS_CFG Table 85. Bit Descriptions for TS_CFG Bits Bit Name Description Reset Access [31:5] RESERVED Reserved. 0x0 R 4 TS_CAPT_FREE_CNT Capture the Free Running Counter. When this bit is 1 and FTSS is 0, the time stamps are captured from the 32-bit free running counter. If this bit is 0 and FTSS is 0, the 32-bit time stamps as defined in the OPEN Alliance MAC-PHY specification are captured. If FTSS is 1, the 64 bit time stamps as defined in the OPEN Alliance MAC-PHY specification are captured. 0x0 R/W 3 TS_TIMER_STOP Stop Toggling the TS_TIMER Output. Write 1 to this field to stop the TS_TIMER output toggling and return it to its default value. Write to the TS_TIMER_START registers to start the TS_TIMER output signal again. This bit automatically clears to 0. 0x0 W 2 TS_TIMER_DEF The Default Value for the TS_TIMER Output. To change the default value of the TS_TIMER from 0, write 1 to this field before enabling the TS_TIMER (it is enabled when TS_TSTART is 0x0 R/W |
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