ADIN1111CCPZ-R7 datasheet(11/109 Pages) AD

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Data Sheet

ADIN1111

THEORY OF OPERATION

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Rev. A | 11 of 109

The ADIN1111 is a low power, single port 10 Mb/s Ethernet MAC-

PHY device, compliant with the IEEE 802.3cg Ethernet standard for

long reach, 10 Mbps single pair Ethernet.

The ADIN1111 integrates the following features:

►

10BASE-T1L Ethernet PHY core and MAC with all the associat-

ed common analog circuitry

►

Input and output clock buffering

►

SPI and subsystem registers

►

Control logic to manage the reset and clock

►

Hardware configuration pins

►

Two configurable LED pins

POWER SUPPLY DOMAINS

The ADIN1111 has three power supply domains and requires a

minimum of one supply rail, as follows:

►

AVDD_H is the analog power supply input for the analog front

end (AFE) circuitry in the ADIN1111.

►

AVDD_L is the analog supply voltage for the internal LDO

circuits. AVDD_L can be connected to the AVDD_H rail when

in single-supply mode, or to an alternative lower voltage rail

when the device is configured with dual supplies for lower power

consumption.

►

VDDIO enables the SPI voltage supply to be configured inde-

pendently of the other circuitry on the ADIN1111. VDDIO can be

connected directly to the AVDD_L rail.

In a single-supply application, connect AVDD_H = AVDD_L =

VDDIO. The appropriate supply voltage used depends on the end

application and cable length. The higher transmit amplitude of

2.4 V p-p requires AVDD_H = 3.3 V, whereas the lower transmit

amplitude of 1.0 V p-p requires AVDD_H = 1.8 V or 3.3 V.

ANALOG FRONT END

The AFE stage consists of a hybrid stage, 9-level DAC, line driver,

analog receive filter, input buffer, and ADC.

The line driver transmits the signal onto the line via the MDI inter-

face pins, TXP and TXN. The hybrid stage subtracts the transmitted

signal from the received signal on the MDI pins, allowing full duplex

operation on the single-pair cable.

The received signal then goes through the analog receive filter and

reaches the input buffer before sending it to the ADC.

MAC

The MAC included in the ADIN1111 supports 16 different MAC

addresses. The MAC also has one low priority receive first in, first

out (FIFO), one high priority receive FIFO and one transmit FIFO.

These FIFOs can ship data in store and forward mode when using

the generic SPI protocol, and in either store and forward or cut

through mode when using the OPEN Alliance protocol.

A generic version and OPEN Alliance version of the SPI protocol

are available. The data is transferred over the SPI half duplex using

the generic SPI protocol and full duplex using the OPEN Alliance

SPI protocol. See the MAC SPI section.

Interrupt (INT)

The ADIN1111 is capable of generating an interrupt to a host pro-

cessor using the INT pin in response to a variety of user selectable

conditions. The following conditions can be selected to generate an

interrupt:

►

Link status change

►

Receive FIFO data available

►

Frame transmit complete or transmit space available

►

Time stamp captured

►

Operation error detected

►

PHY related interrupts

When an interrupt occurs, the system can poll the MAC status

registers (STATUS0 and STATUS1) to determine the origin of the

interrupt.

TRANSMIT AMPLITUDE CONFIGURATION

The ADIN1111 supports two transmit amplitude modes of operation

as follows:

►

1.0 V p-p and 2.4 V p-p mode (high level)

►

1.0 V p-p only mode

The high level transmission mode allows the ADIN1111 to support

both 2.4 V p-p and 1.0 V p-p voltage levels. The operating level can

then be automatically configured during autonegotiation (if enabled)

based on the link partner capabilities. Note that the high level

transmit operating mode of 2.4 V p-p requires an AVDD_H supply

voltage of 3.3 V. Otherwise, if the supply voltage is less than 3.3 V,

the device might not start up correctly.

The mode of operation is configured through the TX2P4_EN hard-

ware configuration pin (see the Transmit Amplitude section). The

ADIN1111 also configures the default value of the transmit level

configured on that pin.

The ADIN1111 is configured in high level transmit operating mode

by default if the TX2P4_EN pin is left floating (internal pull-down

resistor).

LEADER/FOLLOWER CONFIGURATION

The 10BASE-T1L standard uses a leader/follower clock scheme.

This scheme is commonly used in full duplex transceiver standards

with echo cancellation.

On a 10BASE-T1L link, one PHY is designated as the leader, and

the other PHY as the follower. Autonegotiation is used to determine

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