ADIN1111CCPZ-R7 datasheet(9/109 Pages) AD

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Data Sheet

ADIN1111

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. A | 9 of 109

Table 7. Pin Function Descriptions (Hardware Pin Configuration Groupings Are Subject to Change) (Continued)

Pin No.

Mnemonic1

PU/PD2

Description

Configuration/Status

LED_0

Programmable LED Indicator for General-Purpose LED. The LED is active low. The

LED can be active high or active low. By default, LED_0 is configured to turn on when

a link is established and blink when there is activity. See the LED Functions section.

LINK_ST

Link Status Output. LINK_ST indicates whether a valid link is established. LINK_ST is

active high.

LED_1

Programmable LED Indicator for General-Purpose LED. The LED can be active high

or active low. By default, LED_1 is disabled. See the LED Functions section.

TX2P4_EN3

Transmit Level Amplitude Hardware Configuration Pin. Set high for 1.0 V p-p transmit

amplitude only. Set low to support both 1.0 V p-p and 2.4 V p-p transmit amplitude.

See Table 14.

SWPD_EN3

Software Power-Down Configuration. Set low to configure PHY to enter software

power-down mode after power-up/reset. See Table 12.

LDOs and REFERENCE

CEXT_2

N/A

External Decoupling for LDO Circuit. Connect a 0.1 μF capacitor to ground as close as

possible to this pin. Do not use this pin as a voltage source for an external circuit.

CEXT_3

N/A

External Decoupling for LDO Circuit. Connect a 1 μF capacitor to ground as close as

possible to this pin. Do not use this pin as a voltage source for an external circuit.

Power and Ground Pins

AVDD_H

N/A

Analog Supply Voltage for the Various Analog Circuits in the Device. This supply rail

can be supplied by 1.8 V to 3.3 V depending on the transmit level configuration.

If AVDD_H is 3.3 V, both 1.0 V p-p and 2.4 V p-p transmit operating modes are

supported. If AVDD_H is 1.8 V only, then only 1.0 V p-p transmit operating mode is

supported. Connect 0.1 μF and 0.01 μF capacitors to GND as close as possible to this

pin.

AVDD_L

N/A

Analog Supply Voltage for the Internal LDO Circuits. This supply rail can be supplied

by 1.8 V to 3.3 V. AVDD_L can be connected direct to the AVDD_H rail in long reach

applications or to an alternative lower voltage rail when the device is configured with

dual supplies for lower power consumption. Connect 0.1 μF and 0.01 μF capacitors to

GND as close as possible to this pin.

DLDO_1P1

N/A

Digital Core 1.1 V Power Supply Output Pin. Connect a 0.68 μF capacitor to GND as

close as possible to the pin.

VDDIO

N/A

3.3 V, 2.5 V, or 1.8 V Digital Power for SPI. Connect 0.1 μF and 0.01μF capacitors to

GND as close as possible to the pin.

N/A

Exposed Pad. This GND paddle must be connected to ground. The LFCSP package

has an exposed pad that needs to be connected to GND for electrical reasons and

must be soldered to a metal plate on the PCB for mechanical reasons. A 4 × 4 array of

thermal vias beneath the exposed GND pad is also recommended.

Other Pins

9, 10, 14, 17, 27

DNC

N/A

Do Not Connect. These pins must be left open circuit.

TEST1

This pin requires a 1.5 kΩ pull-up resistor to VDDIO.

TEST2

This pin must be left open circuit.

1 Where a pin is shared between a functional signal and a hardware pin configuration, the hardware pin configuration signal is listed last and the pin is referred to using the

functional signals name throughout the data sheet.

2 PU/PD refers to internal/on-chip pull-up or pull-down resistors. The internal pull-up or pull-down resistor is predefined and nonconfigurable. N/A means not applicable

3 All of the hardware configuration pins have internal pull-down resistors. The default mode of operation without any external resistors connected to these pins is shown in

Table 10. If an alternative mode of operation is required, use 4.7 kΩ pull-up resistors.

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