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ADIN1111CCPZ-R7 数据表(PDF) 104 Page - Analog Devices |
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ADIN1111CCPZ-R7 数据表(HTML) 104 Page - Analog Devices |
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104 / 109 page  Data Sheet ADIN1111 REGISTERS analog.com Rev. A | 104 of 109 Table 211. Bit Descriptions for FC_USZ_CNT Bits Bit Name Description Reset Access [15:0] FC_USZ_CNT Latched Copy of the Undersized Frame Error Counter. 0x0 R Frame Checker Odd Nibble Frame Count Register Device Address: 0x1F; Register Address: 0x8010, Reset: 0x0000, Name: FC_ODD_CNT This register is a latched copy of the odd nibble frame register. This register is a count of received frames with an odd number of nibbles in the frame. When the receive error counter (RX_ERR_CNT) is read, the odd nibble frame counter register is latched, which ensures that the odd nibble frame count and the receive frame count are synchronized. Table 212. Bit Descriptions for FC_ODD_CNT Bits Bit Name Description Reset Access [15:0] FC_ODD_CNT Latched Copy of the Odd Nibble Counter. 0x0 R Frame Checker Odd Preamble Packet Count Register Device Address: 0x1F; Register Address: 0x8011, Reset: 0x0000, Name: FC_ODD_PRE_CNT This register is a latched copy of the odd preamble packet counter register. This register is a count of received packets with an odd number of nibbles in the preamble. When the receive error counter (RX_ERR_CNT) is read, the odd preamble packet counter register is latched, which ensures that the odd preamble packet count and the receive frame count are synchronized. Table 213. Bit Descriptions for FC_ODD_PRE_CNT Bits Bit Name Description Reset Access [15:0] FC_ODD_PRE_CNT Latched Copy of the Odd Preamble Packet Counter. 0x0 R Frame Checker False Carrier Count Register Device Address: 0x1F; Register Address: 0x8013, Reset: 0x0000, Name: FC_FALSE_CARRIER_CNT This register is a latched copy of the false carrier events counter register. This is a count of the number of times the bad SSD state is entered. When the receive error counter (RX_ERR_CNT) is read, the false carrier events counter register is latched, which ensures that the false carrier events count and the receive frame count are synchronized. Table 214. Bit Descriptions for FC_FALSE_CARRIER_CNT Bits Bit Name Description Reset Access [15:0] FC_FALSE_CARRIER_CNT Latched Copy of the False Carrier Events Counter. 0x0 R Frame Generator Enable Register Device Address: 0x1F; Register Address: 0x8020, Reset: 0x0000, Name: FG_EN This register is used to enable the frame generator. When the frame generator is enabled, the source of data for the PHY comes from the frame generator and not the MAC interface. To use the frame generator, the diagnostic clock must also be enabled (DIAG_CLK_EN). Table 215. Bit Descriptions for FG_EN Bits Bit Name Description Reset Access [15:1] RESERVED Reserved. 0x0 R 0 FG_EN Frame Generator Enable. 0x0 R/W |
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