ST10F272M datasheet(92/175 Pages) STMICROELECTRONICS

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System reset

ST10F272M

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The Bidirectional reset is not effective in case RPD is held low, when a Software or

Watchdog reset event occurs. On the contrary, if a Software or Watchdog Bidirectional reset

event is active and RPD becomes low, the RSTIN pin is immediately released, while the

internal reset sequence is completed regardless of RPD status change (1024 TCL).

Note:

The bidirectional reset function is disabled by any reset sequence (bit BDRSTEN of

SYSCON is cleared). To be activated again it must be enabled during the initialization

routine.

WDTCON flags

Similar to what is highlighted in the previous section, when discussing Short reset and the

degeneration into Long reset, comparable situations may occur when Bidirectional reset is

enabled. The presence of the internal filter on RSTIN pin introduces a delay: When RSTIN is

released, the internal signal after the filter (see RSTF in the drawings) is delayed, so it

remains still active (low) for a while. It means that depending on the internal clock speed, a

short reset may be recognized as a long reset: The WDTCON flags are set accordingly.

Moreover, when either Software or Watchdog bidirectional reset events occur, when the

RSTIN pin is released (at the end of the internal reset sequence), the RSTF internal signal

(after the filter) remains low for a while, and depending on the clock frequency it is

recognized high or low: 8TCL after the completion of the internal sequence, the level of

RSTF signal is sampled, and if recognized still low a Hardware reset sequence starts, and

WDTCON will flag this last event, masking the previous one (Software or Watchdog reset).

Typically, a Short Hardware reset is recognized, unless the RSTIN pin (and consequently

internal signal RSTF) is sufficiently held low by the external hardware to inject a Long

Hardware reset. After this occurrence, the initialization routine is not able to recognize a

Software or Watchdog bidirectional reset event, since a different source is flagged inside

WDTCON register. This phenomenon does not occur when internal Flash is selected during

reset (EA = 1), since the initialization of the Flash itself extend the internal reset duration

well beyond the filter delay.

The next Figures 27, 28 and 29 summarize the timing for Software and Watchdog Timer

Bidirectional reset events: In particular Figure 29 shows the degeneration into Hardware

reset.

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