AS3953B datasheet(24/65 Pages) AMSOSRAM

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[v1-04] 2016-Jan-07

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AS3953B − Detailed Description

Therefore, if the EEPROM programming is executed, the

AS3953B reply comes after 8ms typical. Figure below defines

the coding of the AS3953B reply to Write EEPROM command.

Figure 32:

Write EEPROM Reply

Passing of Block Data to Controller

After the PICC Logic has passed the anti-collision procedure and

replied with SAK on Cascade Level 2 it passes in ACTIVE(*) state.

On this level it expects that blocks received from the PCD have

the format according to ISO 14443A-4. The ISO 144443A Logic

recognizes the command by observing the first received byte.

Based on content of this byte command is either processed by

the AS3953B or the complete block data is put in the FIFO for

further processing by the controller. The figure below displays

the decision criteria.

Information Field

Comment

90h

Writing is normally processed

61h

Writing is not done due to coding

error (error in parity, CRC, nonexistent

address…)

62h

Writing is not done since the word is

locked

64h

Writing is not done due to power

check fail

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