AS3953B datasheet(41/65 Pages) AMSOSRAM

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[v1-04] 2016-Jan-07

AS3953B − Application Information

Interrupt Interface

There are two interrupt registers implemented in the AS3953B

(Main Interrupt Register and Auxiliary Interrupt Register). Main

Interrupt Register contains information about seven interrupt

sources, while one bit references to interrupt sources detailed

in Auxiliary Interrupt Register.

When an interrupt condition is met the source of interrupt bit

is set in the Main Interrupt Register and the IRQ pin transitions

to high.

The controller then reads the Main Interrupt Register to

distinguish between different interrupt sources. In case the bit

l_aux is pointing to the Auxiliary Interrupt Register, this register

also needs to be read. After an interrupt register (main or

auxiliary) is read its content is reset to ‘0’. Exception to this rule

is the bit pointing to auxiliary register. This bit is only cleared

when the auxiliary interrupt register is read. IRQ pin transitions

to high after the interrupt bit(s) which caused its transition to

high has been read. Please note that there may be more than

one interrupt register bit set in case the controller did not

immediately read the Interrupt registers after the IRQ signal is

set and another event causing interrupt occurred.

FIFO Water Level and FIFO Status Register

The AS3953B contains a 32 byte FIFO. In case of transmitting

the Control logic shifts data which was previously loaded by the

external controller to the Framing Block and further to the

Transmitter. During reception, the demodulated data is stored

in the FIFO and the external controller can download received

data.

Transmit and receive capability of the AS3953B is not limited

by of the FIFO size due to a FIFO water level interrupt system.

During transmission an interrupt is sent (interrupt due to FIFO

water level in the Main Interrupt Register) when the content of

data in the FIFO which still need to be sent is lower than the

FIFO water level for transmit. The external controller can now

add more data in the FIFO. The same stands for receive mode.

In case the number of received bytes increases over the FIFO

water level for receive an interrupt is sent to inform the external

controller that data has to be downloaded from FIFO.

The external controller has to serve the FIFO faster than data is

transmitted or received. A general rule is that the SCLK

frequency has to be at least double than the actual data rate in

receive or transmit.

FIFO water level is set to ¾ of FIFO for reception and to ¼ of

FIFO for transmission. This means that in case of getting an

interrupt during reception there are already 24 bytes in the

FIFO, which have to be read out to liberate space for following

data bytes. Same stands for transmission, water level interrupt

is sent when there are 8 bytes left in FIFO, therefore up to 24

additional bytes can be loaded.

AS3953B 数据表(PDF) 41 Page - ams-OSRAM AG

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