AS3953B datasheet(42/65 Pages) AMSOSRAM

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[v1-04] 2016-Jan-07

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AS3953B − Application Information

During FIFO operation (FIFO read or FIFO load) the water level

detection system is blocked to avoid spurious water level

interrupts (these might occur when for example number of

bytes has increased above water level during loading and

immediately after that dropped again below water level due to

Tx process which runs in parallel). Due to this the FIFO

loading/reading rate has to be higher than Tx / Rx bit rate, once

FIFO loading/reading is finished the /SS pin has to be pulled to

VDD (logic remains in FIFO load/read mode as long as /SS

remains low).

In case loading/reading of FIFO is not much faster than Tx / Rx

processes low the following two cases have to be considered:

• FIFO underflow IRQ is not blocked, in case loading in FIFO

is slower than transmission process the FIFO underflow

IRQ is produced.

• In case of slow FIFO loading it is possible that the content

of FIFO is increased above water level but it is below when

FIFO loading is finished. In such case a water level IRQ is

issued after termination of FIFO loading. Same stands for

FIFO reading.

• In case of slow FIFO loading it is possible that the content

of FIFO stays below water level during complete FIFO

loading operation. In such case water level IRQ is not

issued after termination of FIFO loading. Same stands for

FIFO reading.

• In case it is known that the receive data frame is smaller

than the FIFO size the water level interrupt does not have

to be served. In such case the water level interrupt can be

masked.

• After data is received the external controller needs to

know how long the receive data string was before

downloading data from the FIFO: This information is

available in the FIFO Status Register 1 and FIFO Status

were not read out.

The FIFO Status Register 2 additionally contains two bits which

indicate that the FIFO was not correctly served during reception

or transmission process (FIFO overflow and FIFO underflow).

FIFO overflow is set when too much data is written in FIFO. In

case this bit is set during reception the external controller did

not react on time on water level IRQ and more than 32 bytes

were written in the FIFO. The received data is corrupted in such

a case. During transmission this means that controller has

written more data than FIFO size. The data to be transmitted is

corrupted.

FIFO underflow is set when data was read from empty FIFO. In

case this bit is set during reception the external controller read

more data than was actually received. During transmission this

means that controller has failed to provide the quantity of data

defined in number of transmitted bytes registers on time.

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