AS3953B datasheet(51/65 Pages) AMSOSRAM

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[v1-04] 2016-Jan-07

AS3953B − Application Information

Interrupt Register and Associated Registers

Figure 59:

Mask Main Interrupt Register

Note(s):

1. Default setting is set at power-up and after Set Default command.

Address# 08h : Mask Main Interrupt

Type: RW

Bit

Name

Default

Function

Comments

M_pu

Mask power-up IRQ

This bit is set to ‘0’ during

power-up initialization in case

EEPROM configuration bit irq_

pu is set to ‘1’

M_wu_l4

Mask wake-up IRQ at entry in

ACTIVE(*) state

This bit is set to ‘0’ during

power-up initialization in case

EEPROM configuration bit irq_

l4 is set to ‘1’

5M_wu

Mask wake-up IRQ triggered

by sending Wake-Up

command

4M_rxs

Mask IRQ due to start of

receive

3M_rxe

Mask IRQ due to end of

receive

M_txe

Mask IRQ due to end of

transmission

1M_wl

Mask IRQ due to FIFO water

level

RFU

AS3953B 数据表(PDF) 51 Page - ams-OSRAM AG

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