ADBMS1818CSWAZ-R7 datasheet(41/92 Pages) AD

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Data Sheet

ADBMS1818

THEORY OF OPERATION

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Rev. B | 41 of 92

The default values of the PWM control settings (located in PWM

Upon entering sleep mode, the PWM control settings are initialized

to their default values.

DISCHARGE TIMER MONITOR

The ADBMS1818 has the ability to periodically monitor cell voltages

while the discharge timer is active. The host writes the DTMEN bit

in Configuration Register Group B to 1 to enable this feature.

When the discharge timer monitor is enabled and the watchdog

timer has expired, the ADBMS1818 performs a conversion of all cell

voltages in 7 kHz (normal) mode every 30 seconds. The overvolt-

age and undervoltage comparisons are performed and flags are set

if cells have crossed a threshold. For any undervoltage cells, the

discharge timer monitor automatically clears the associated DCC bit

in Configuration Register Group A or Configuration Register Group

B so that the cell is no longer discharged. Clearing the DCC bit also

disables PWM discharge. With this feature, the host can write the

undervoltage threshold to the desired discharge level and use the

discharge timer monitor to discharge all, or selected, cells (using

either constant discharge or PWM discharge) down to that level.

During discharge timer monitoring, digital redundancy checking is

performed on the cell voltage measurements. If a digital redundan-

cy failure occurs, all DCC bits are cleared.

I2C/SPI MASTER ON ADBMS1818 USING

GPIOS

The I/O ports GPIO3, GPIO4, and GPIO5 on the ADBMS1818 can

be used as an I2C or SPI master port to communicate to an I 2C or

SPI slave. In the case of an I2C master, GPIO4 and GPIO5 form the

SDA and SCL ports of the I2C interface, respectively. In the case of

an SPI master, GPIO3, GPIO4, and GPIO5 are the CSBM, SDIOM,

and SCKM ports of the SPI, respectively. The SPI master on the

ADBMS1818 supports SPI Mode 3 (CHPA = 1 and CPOL = 1).

The GPIOs are open-drain outputs, so an external pull-up is re-

quired on these ports to operate as an I2C or SPI master. It is also

important to write the GPIO bits to 1 in the configuration register

groups so these ports are not pulled low internally by the device.

COMM Register

ADBMS1818 has a 6-byte COMM register, as shown in Table 36.

This register stores all data and control bits required for I2C or

SPI communication to a slave. The COMM register contains three

bytes of data Dn, Bits[7:0] to be transmitted to or received from

the slave device. ICOMn, Bits[3:0] specify control actions before

transmitting/receiving each data byte. FCOMn, Bits[3:0] specify

control actions after transmitting/receiving each data byte.

If ICOMn, Bit 3 in the COMM register is set to 1, the device

becomes an SPI master, and if the bit is set to 0, the device

becomes an I2C master.

Table 37 describes the valid write codes for ICOMn, Bits[3:0] and

FCOMn, Bits[3:0] and their behavior when using the device as an

I2C master.

Table 38 describes the valid write codes for ICOMn, Bits[3:0] and

FCOMn, Bits[3:0] and their behavior when using the device as an

SPI master.

Note that only the codes listed in Table 37 and Table 38 are valid

for ICOMn, Bits[3:0] and FCOMn, Bits[3:0]. Writing any other code

that is not listed in Table 37 and Table 38 to ICOMn, Bits[3:0] and

FCOMn, Bits[3:0] may result in unexpected behavior on the I2C or

SPI port.

Table 36. COMM Register Memory Map

R/W

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

COMM0

R/W

ICOM0, Bit 3

ICOM0, Bit 2

ICOM0, Bit 1

ICOM0, Bit 0

D0, Bit 7

D0, Bit 6

D0, Bit 5

D0, Bit 4

COMM1

R/W

D0, Bit 3

D0, Bit 2

D0, Bit 1

D0, Bit 0

FCOM0, Bit 3

FCOM0, Bit 2

FCOM0, Bit 1

FCOM0, Bit 0

COMM2

R/W

ICOM1, Bit 3

ICOM1, Bit 2

ICOM1, Bit 1

ICOM1, Bit 0

D1, Bit 7

D1, Bit 6

D1, Bit 5

D1, Bit 4

COMM3

R/W

D1, Bit 3

D1, Bit 2

D1, Bit 1

D1, Bit 0

FCOM1, Bit 3

FCOM1, Bit 2

FCOM1, Bit 1

FCOM1, Bit 0

COMM4

R/W

ICOM2, Bit 3

ICOM2, Bit 2

ICOM2, Bit 1

ICOM2, Bit 0

D2, Bit 7

D2, Bit 6

D2, Bit 5

D2, Bit 4

COMM5

R/W

D2, Bit 3

D2, Bit 2

D2, Bit 1

D2, Bit 0

FCOM2, Bit 3

FCOM2, Bit 2

FCOM2, Bit 1

FCOM2, Bit 0

Table 37. Write Codes for ICOMn, Bits[3:0] and FCOMn, Bits[3:0] on I2C Master

Control Bits

Code

Action

Description

ICOMn, Bits[3:0]

0110

Start

Generate a start signal on I2C port followed by a data transmission

0001

Stop

Generate a stop signal on I2C port

0000

Blank

Proceed directly to data transmission on I2C port

0111

No transmit

Release SDA and SCL and ignore the rest of the data

FCOMn, Bits[3:0]

0000

Master ACK

Master generates an ACK Signal on ninth clock cycle

1000

Master NACK

Master generates a NACK signal on ninth clock cycle

1001

Master NACK + stop

Master generates a NACK signal followed by a stop signal

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