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ADBMS1818CSWAZ-R7 数据表(PDF) 45 Page - Analog Devices |
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ADBMS1818CSWAZ-R7 数据表(HTML) 45 Page - Analog Devices |
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45 / 92 page  Data Sheet ADBMS1818 THEORY OF OPERATION analog.com Rev. B | 45 of 92 Timing Specifications of I2C and SPI Master The timing of the ADBMS1818 I2C or SPI master is controlled by the timing of the communication at the primary SPI of the ADBMS1818. Table 40 shows the I2C master timing relationship to the primary SPI clock. Table 41 shows the SPI master timing specifications. Table 40. I2C Master Timing I2C Master Parameter Timing Relationship to Primary SPI Timing Specifications at tCLK = 1 μs SCL Clock Frequency 1/(2 × tCLK) 500 kHz maximum tHD, STA t3 200 ns minimum tLOW tCLK 1 μs minimum tHIGH tCLK 1 μs minimum tSU, STA tCLK + t41 1.03 μs minimum tHD, DAT t4 30 ns minimum tSU, DAT t3 200 ns minimum tSU, STO tCLK + t4 1 1.03 μs minimum tBUF 3 × tCLK 3 μs minimum 1 When using isoSPI, t4 is generated internally and is a minimum of 30 ns. Also, t3 = tCLK – t4. When using SPI, t3 and t4 are the low and high times of the SCK input, each with a specified minimum of 200 ns. Table 41. SPI Master Timing SPI Master Parameter Timing Relationship to Primary SPI Timing Specifications at tCLK = 1 μs SDIOM Valid to SCKM Rising Setup t3 200 ns minimum SDIO Valid from SCKM Rising Hold tCLK + t41 1.03 μs minimum SCKM Low tCLK 1 μs minimum SCKM High tCLK 1 μs minimum SCKM Period (SCKM_Low + SCKM_High) 2 × tCLK 2 μs minimum CSBM Pulse Width 3 × tCLK 3 μs minimum SCKM Rising to CSBM Rising 5 × tCLK + t4 1 5.03 μs minimum CSBM Falling to SCKM Falling t3 200 ns minimum CSBM Falling to SCKM Rising tCLK + t3 1.2 μs minimum SCKM Falling to SDIOM Valid Master Requires < tCLK 1 When using isoSPI, t4 is generated internally and is a minimum of 30 ns. Also, t3 = tCLK – t4. When using SPI, t3 and t4 are the low and high times of the SCK input, each with a specified minimum of 200 ns. S PIN PULSING USING THE S PIN CONTROL SETTINGS The S pins of the ADBMS1818 can be used as a simple serial interface, which is particularly useful for controlling the LT8584, a monolithic flyback dc-to-dc converter, designed to actively balance large battery stacks. The LT8584 has several operating modes which are controlled through a serial interface. The ADBMS1818 can communicate to an LT8584 by sending a sequence of pulses on each S pin to select a specific LT8584 mode. The S pin control settings (located in S Control Register Group and PWM/S Control Register Group B) are used to specify the behavior for each of the 18 S pins, where each nibble specifies whether the S pin drives high, drives low, or sends a pulse sequence between 1 and 7 pulses. The figures in this section show the possible S pin behaviors that can be sent to the LT8584. The S pin pulses occur at a pulse rate of 6.44 kHz (155 μs period). The pulse width is 77.6 μs. The S pin pulsing begins when the STSCTRL command is sent, after the last command PEC clock, provided that the command PEC matches. The host can then continue to clock SCK in order to poll the status of the pulsing. This polling works similarly to the ADC polling feature. The data out remains logic low until the S pin pulsing sequence completes. While the S pin pulsing is in progress, new STSCTRL, WRSCTRL, or WRPSB commands are ignored. The PLADC command can be used to determine when the S pin pulsing completes. If the WRSCTRL (or WRPSB) command and command PEC are received correctly but the data PEC does not match, the S pin control settings are cleared. If a DCC bit in Configuration Register Group A or Configuration Register Group B is asserted, the ADBMS1818 drives the selected S pin low, regardless of the S pin control settings. The host must leave the DCC bits set to 0 when using the S pin control settings. The CLRSCTRL command can be used to quickly reset the S pin control settings to all 0s and force the pulsing machine to release control of the S pins. This command can be helpful in reducing the diagnostic control loop time in a high reliability application. The following figures show the S pin pulsing behavior. Figure 67. S Pin Behavior when S Pin Control Bits = 0000 |
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