ADBMS1818CSWAZ-R7 datasheet(47/92 Pages) AD

47 / 92 page

Data Sheet

ADBMS1818

THEORY OF OPERATION

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Rev. B | 47 of 92

S PIN MUTING

The S pins can be disabled by sending the mute command and

reenabled by sending the unmute command. The mute and un-

mute commands do not require any subsequent data and thus

the commands propagate quickly through a stack of ADBMS1818

devices. This action allows the host to quickly (<100 µs) disable

and reenable discharging without disturbing register contents. This

ability can be useful, for instance, to allow a specific settling time

before taking cell measurements. The mute status is reported in the

read-only MUTE bit in Configuration Register Group B.

SERIAL INTERFACE OVERVIEW

There are two types of serial ports on the ADBMS1818: a standard

4-wire SPI and a 2-wire isoSPI. The state of the ISOMD pin

determines whether Pin 53, Pin 54, Pin 61, and Pin 62 are a 2-wire

or 4-wire serial port.

The ADBMS1818 is used in a daisy-chain configuration.

A second isoSPI uses Pin 57, Pin 58, Pin 63, and Pin 64.

4-WIRE SERIAL PERIPHERAL INTERFACE

(SPI) PHYSICAL LAYER

External Connections

Connecting ISOMD to V– configures serial Port A for 4-wire SPI.

The SDO pin is an open drain output that requires a pull-up resistor

tied to the appropriate supply voltage (see Figure 76).

Figure 76. 4-Wire SPI Configuration

Timing

The 4-wire serial port is configured to operate in an SPI system

using CPHA = 1 and CPOL = 1. Consequently, data on SDI must

be stable during the rising edge of SCK. The timing is depicted in

Figure 77. The maximum data rate is 1 Mbps. However, the device

is tested at a higher data rate in production to guarantee operation

at the maximum specified data rate.

2-WIRE ISOLATED INTERFACE (ISOSPI)

PHYSICAL LAYER

The 2-wire interface provides a means to interconnect ADBMS1818

devices using simple twisted pair cabling. The interface is designed

for low packet error rates when the cabling is subjected to high RF

fields. Isolation is achieved through an external transformer.

Standard SPI signals are encoded into differential pulses. The

strength of the transmission pulse and the threshold level of the re-

ceiver are set by two external resistors. The values of the resistors

allow the user to trade-off power dissipation for noise immunity.

Figure 78 shows how the isoSPI circuit operates. A 2 V reference

drives the IBIAS pin. External resistors RB1 and RB2 create the

reference current, IB. This current sets the drive strength of the

transmitter. RB1 and RB2 also form a voltage divider to supply a

fraction of the 2 V reference for the ICMP pin. The receiver circuit

threshold is half of the voltage at the ICMP pin.

External Connections

The ADBMS1818 has 2 serial ports, Port B and Port A. Port B is

always configured as a 2-wire interface. Port A is either a 2-wire or

4-wire interface, depending on the connection of the ISOMD pin.

When Port A is configured as a 4-wire interface, Port A is always

the slave port and Port B is the master port. Communication is

always initiated on Port A of the first device in the daisy-chain

configuration. The final device in the daisy chain does not use

Port B, and it must be terminated into RM. Figure 79 shows the

simplest port connections possible when the microprocessor and

the ADBMS1818s are located on the same PCB. In Figure 79,

capacitors are used to couple signals between the ADBMS1818s.

When Port A is configured as a 2-wire interface, communication

can be initiated on either Port A or Port B. If communication is

initiated on Port A, ADBMS1818 configures Port A as a slave and

Port B as a master. Likewise, if communication is initiated on Port

B, ADBMS1818 configures Port B as a slave and Port A as a

master. See the Reversible isoSPI section for a detailed description

of the reversible isoSPI.

Figure 80 is an example of a robust interconnection of multiple

identical PCBs, each containing one ADBMS1818 configured for

operation in a daisy chain. The microprocessor is located on a sep-

arate PCB. To achieve 2-wire isolation between the microprocessor

PCB and the 1st ADBMS1818 PCB, use the LTC6820 support IC.

The LTC6820 is functionally equivalent to the diagram in Figure 78.

In this example, communication is initiated on Port A. Therefore, the

ADBMS1818 configures Port A as a slave and Port B as a master.

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