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AX88772ALF 数据表(PDF) 30 Page - ASIX Electronics Corporation |
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AX88772ALF 数据表(HTML) 30 Page - ASIX Electronics Corporation |
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30 / 45 page ![]() ASIX ELECTRONICS CORPORATION 30 AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller 9.4.4 MII Timing Tth Tts Ttcl k Ttcl Ttcl k Ttcl Ttch Ttch TXCLK TXEN / TXD[3:0] Symbol Description Min Typ Max Unit Ttclk TXCLK clock cycle time *1 - 40.0 - ns Ttch TXCLK clock high time *2 - 20.0 - ns Ttcl TXCLK clock low time *2 - 20.0 - ns Tts TXD [3:0], TXEN setup to rising TXCLK 23.0 - - ns Tth TXD [3:0], TXEN hold from rising TXCLK 7.0 - - ns Trh Trs Trclk Trcl Trclk Trcl Trch Trch RXCLK RXDV / RXD[3:0] Symbol Description Min Typ Max Unit Trclk RXCLK clock cycle time *1 - 40.0 - ns Trch RXCLK clock high time *2 - 20.0 - ns Trcl RXCLK clock low time *2 - 20.0 - ns Trs RXD [3:0], RXDV setup to rising RXCLK 5.0 - - ns Trh RXD [3:0], RXDV hold from rising TXCLK 3.5 - - ns *1: For 10Mbps, the typical value of Ttclk and Trclk shall scale to 400ns. *2: For 10Mbps, the typical value of Ttch, Ttcl, Trch, and Trcl shall scale to 200ns. |
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