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AX88772ALF 数据表(PDF) 39 Page - ASIX Electronics Corporation |
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AX88772ALF 数据表(HTML) 39 Page - ASIX Electronics Corporation |
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39 / 45 page ![]() ASIX ELECTRONICS CORPORATION 39 AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller Dynamic Characteristic for Analog I/O Pins (DP/DM): Symbol Parameter Conditions Min Typ Max Unit Driver Characteristic High-Speed Mode tHSR High-speed differential rise time - 500 - - ps tHSF High-speed differential fall time - 500 - - ps Full-Speed Mode tFR Rise time of DP/DM CL=50pF; 10 to 90% of |VOH - VOL| 4 - 20 ns tFF Fall time of DP/DM CL=50pF; 90 to 10% of |VOH - VOL| 4 - 20 ns tFRMA Differential rise/fall time matching ( tFR / tFF) Excluding the first transition from idle mode 90 - 110 % VCRS Output signal crossover voltage Excluding the first transition from idle mode 1.3 - 2.0 V Driver Timing High-Speed Mode Driver waveform requirement See eye pattern of template 1 Follow template 1 described in USB rev 2.0 spec. (http://www.usb.org/developers/docs ) Full-Speed Mode VI, FSE 0, OE to DP, DN Propagation delay For detailed description of VI, FSE 0 and OE, please refer to USB rev 1.1specification. - - 15 ns Receiver Timing High-Speed Mode Data source jitter and receiver jitter tolerance See eye pattern of template 4 Follow template 4 described in USB rev 2.0 spec. (http://www.usb.org/developers/docs ) Full-Speed Mode tPLH(rcv) tPHL (rcv) Receiver propagation delay (DP; DM to RCV) For detailed description of RCV, please refer to USB rev 1.1specification. - - 15 (Note) ns tPLH(single) tPHL(single) Receiver propagation delay (DP; DM to VOP, VON) - - - 15 (Note) ns Note: Full-Speed Timing diagram |
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