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AX88772ALF 数据表(PDF) 7 Page - ASIX Electronics Corporation |
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AX88772ALF 数据表(HTML) 7 Page - ASIX Electronics Corporation |
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7 / 45 page ![]() ASIX ELECTRONICS CORPORATION 7 AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller 7.1.4 PHY Identifier Register 2.......................................................................................................................... 21 7.1.5 Auto Negotiation Advertisement Register (ANAR) ................................................................................... 21 7.1.6 Auto Negotiation Link Partner Ability Register (ANLPAR) ..................................................................... 21 7.1.7 Auto Negotiation Expansion Register (ANER) ......................................................................................... 21 8.0 STATION MANAGEMENT REGISTERS IN PHY/DUAL-PHY MODE ...........................................................................................................21 8.1 PHY/DUAL-PHY MODE DETAILED REGISTER DESCRIPTION ............................................................................ 21 8.1.1 PHY Mode Basic Mode Control Register (PM_BMCR) ........................................................................... 21 8.1.2 PHY Mode Basic Mode Status Register (PM_BMSR) .............................................................................. 21 8.1.3 PHY Mode PHY Identifier Register 1 ....................................................................................................... 21 8.1.4 PHY Mode PHY Identifier Register 2 ....................................................................................................... 21 8.1.5 PHY Mode Auto Negotiation Advertisement Register (PM_ANAR) ......................................................... 21 8.1.6 PHY Mode Auto Negotiation Link Partner Ability Register (PM_ANLPAR) ........................................... 21 8.1.7 PHY Mode Auto Negotiation Expansion Register (PM_ANER) ............................................................... 21 8.1.8 PHY Mode Control Register (PM_Control) ............................................................................................. 21 9.0 ELECTRICAL SPECIFICATIONS ............................................................22 9.1 DC CHARACTERISTICS ...................................................................................................................................... 22 9.1.1 Absolute Maximum Ratings ...................................................................................................................... 22 9.1.2 Recommended Operating Condition......................................................................................................... 22 9.1.3 Leakage Current and Capacitance ........................................................................................................... 23 9.1.4 DC Characteristics of 3.3V I/O Pins ........................................................................................................ 23 9.1.5 DC Characteristics of 3.3V with 5V Tolerance I/O Pins .......................................................................... 24 9.1.6 DC Characteristics of Voltage Regulator................................................................................................. 25 9.2 POWER CONSUMPTION ...................................................................................................................................... 26 9.3 POWER-UP SEQUENCE ....................................................................................................................................... 27 9.4 AC TIMING CHARACTERISTICS.......................................................................................................................... 28 9.4.1 Clock Timing............................................................................................................................................. 28 9.4.2 Reset Timing ............................................................................................................................................. 28 9.4.3 Serial EEPROM Timing............................................................................................................................ 29 9.4.4 MII Timing ................................................................................................................................................ 30 9.4.5 Station Management Timing..................................................................................................................... 31 9.4.6 Reverse-MII Timing .................................................................................................................................. 32 9.4.7 Reverse-RMII Timing................................................................................................................................ 33 9.4.8 I2C Interface Timing................................................................................................................................. 34 9.4.9 SPI Interface Timing................................................................................................................................. 35 9.4.10 10/100M Ethernet PHY Interface Timing ................................................................................................. 37 9.4.11 USB Transceiver Interface Timing ........................................................................................................... 38 10.0 PACKAGE INFORMATION ...........................................................................40 10.1 AX88772A 64-PIN LQFP PACKAGE.................................................................................................................. 40 10.2 AX88172A 80-PIN TQFP PACKAGE.................................................................................................................. 41 11.0 ORDERING INFORMATION........................................................................42 12.0 REVISION HISTORY................................................................................................43 APPENDIX A. DEFAULT WOL READY MODE .................................................................... 44 |
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