| 数据搜索系统,热门电子元器件搜索 |
|
AX88772ALF 数据表(PDF) 9 Page - ASIX Electronics Corporation |
|
|
|||||||||||||||||||||||||||||
AX88772ALF 数据表(HTML) 9 Page - ASIX Electronics Corporation |
|
9 / 45 page ![]() ASIX ELECTRONICS CORPORATION 9 AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller 1.0 Introduction 1.1 General Description The AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet controller is a high performance and highly integrated ASIC which enables low cost, small form factor, and simple plug-and-play Fast Ethernet network connection capability for desktops, notebook PC’s, Ultra-Mobile PC’s, docking stations, game consoles, digital-home appliances, and any embedded system using a standard USB port. The AX88772A/AX88172A features a USB interface to communicate with a USB Host Controller and is compliant with USB specification V1.1 and V2.0. The AX88772A/AX88172A implements a 10/100Mbps Ethernet LAN function based on IEEE802.3, and IEEE802.3u standards with 24KB of embedded SRAM for packet buffering. The AX88772A/AX88172A integrates an on-chip 10/100Mbps Ethernet PHY to simplify system design. The AX88172A provides an optional External Media Interface (EMI) for external PHY or external MAC for different application purposes. The EMI can be a media-independent interface (MII) for implementing 100BASE-FX Ethernet or HomePNA functions. The EMI can also be a Reverse-MII or Reverse Reduced-MII (Reverse-RMII) for glueless MAC-to-MAC connections to any MCU with Ethernet MAC MII or RMII interface. In addition, the EMI can be configured to Dual-PHY mode allowing AX88172A to act as an Ethernet PHY or USB 2.0 PHY for external MAC device that needs Ethernet and USB interfaces in their system applications. The optional serial interface such as I2C, SPI, and UART are provided as a control channel from the USB Host Controller to communicate with the external MCU chip. The AX88772A/AX88172A needs 12MHz clock for USB operation and 25Mhz clock for Fast Ethernet operation. The AX88772A is housed in the 64-pin LQFP and the AX88172A is housed in the 80-pin TQFP RoHS compliant package. 1.2 Block Diagram Figure 7 : AX88772A/AX88172A Block Diagram DP/DM RXIP/RXIN TXOP/TXON GPIO_2~0 MAC Core Memory Arbiter USB to Ethernet Bridge USB Core and Interfaces STA SEEPROM Loader I/F EECS EECK EEDIO 24KB SRAM General Purpose I/O 10/100M Ethernet PHY Serial I/F Controller: UART/I2C/SPI SI_3~0 AX88172A only External Media Interface MII / Reverse-MII / Reverse-RMII MDC / MDIO 3.3 to 1.8V Regulator PLL Clock Generators Power-On-Reset & Reset Gen. RESET_N XTL25P, XTL25N XTL12P, XTL12N PHY/MAC mode Bridge |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |