ASIX ELECTRONICS CORPORATION

35

AX88772A/AX88172A

Low-pin-count

USB 2.0 to 10/100M Fast Ethernet Controller

9.4.9

SPI Interface Timing

Note: Above diagram only shows setup and hold time relationship of SPI pins in Mode 0. For the remaining 3 modes,

clock polarity is reversed.

SPI Master Controller Timing Table:

Symbol

Description

Min

Typ

Max

Unit

Fclk

SPI_SCLK clock frequency.

-

Fsys_clk/

(SPIBRR+1)*2

5

MHz

(Note 3)

Tl

Setup time of SPI_SS to the first SPI_SCLK edge.

-

0.5

-

Tclk

(Note 3)

Th

Hold time of SPI_SS after the last SPI_SCLK edge.

-

0.5

-

Tclk

Tdly

SPI_MOSI data valid time after SPI_SCLK edge.

-

-

1

Tsys_clk

(Note 4)

Dsu

SPI_MISO data setup time before SPI_SCLK edge.

2

-

-

Tsys_clk

Dhd

SPI_MISO data hold time after SPI_SCLK edge.

4

-

-

Tsys_clk

tl

Minimum idle time between transfers (minimum

SPI_SS high time).

Note 5

Internal time base period.

-

0.5

-

Tclk

Note 3: Fsys_clk is the operating system clock frequency 30Mhz. The SPIBRR is SPI Baud Rate Register.

Tclk = 1/Fclk.

Note 4: Tsys_clk =1/ Fsys_clk =33.33 ns.

Note 5: It will be much greater than 22us because several factors can influence this parameter, such as USB system

utilization, the CBW structure, and High/Full speed ,etc.