AX88796BLF datasheet(19/82 Pages) ASIX

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ASIX ELECTRONICS CORPORATION

AX88796BLF / AX88796BLI

Transmit Packet Assembly

The AX88796B requires a contiguous assembled packet with the format shown below. The transmit byte count

includes the Destination Address, Source Address, Length Field and Data. It does not include preamble and CRC.

When transmitting data smaller than 64 bytes, AX88796B can auto padding to a minimum length of 64 bytes

Ethernet frame. The packets are placed in the buffer RAM by the system. System programs the AX88796B Core's

Remote DMA to move the data from the system buffer RAM to internal transmit buffer RAM.

The data transfer must be 16-bits (1 word) when in 16-bit mode, and 8-bits when the AX88796B Controller is set in

8-bit mode. The data width is selected by setting the WTS bit in the Data Configuration Register.

Destination Address

6 Bytes

Source Address

6 Bytes

Length / Type

2 Bytes

Data

(Pad if < 46 Bytes)

46 Bytes

Min.

General Transmit Packet Format

Transmission

Prior to transmission, the TPSR (Transmit Page Start Register) and TBCR0, TBCR1 (Transmit Byte Count

Registers) must be initialized. To initiate transmission of the packet the TXP bit in the Command Register is set. The

Transmit Status Register (TSR) is cleared and the AX88796B begins to pre-fetch transmit data from memory. If the

Inter-packet Gap (IPG) has timed out the AX88796B will begin transmission.

Conditions Required To Begin Transmission

In order to transmit a packet, the following three conditions must be met:

1. The Inter-packet Gap Timer has timed out

2. At least one byte has entered the FIFO.

3. If a collision had been detected then before transmission the packet back-off time must have timed out.

Collision Recovery

During transmission, the Buffer Management logic monitors the transmit circuitry to determine if a collision has

occurred. If a collision is detected, the Buffer Management logic will reset the FIFO and restore the Transmit DMA

pointers for retransmission of the packet. The COL bit will be set in the TSR and the NCR (Number of Collisions

the ABT bit in the TSR will be set.

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