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AX88796BLF 数据表(PDF) 35 Page - ASIX Electronics Corporation

部件名 AX88796BLF
功能描述  Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller
PDF  82 Pages
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制造商  ASIX [ASIX Electronics Corporation]
网页  http://www.asix.com.tw
标志 ASIX - ASIX Electronics Corporation

AX88796BLF 数据表(HTML) 35 Page - ASIX Electronics Corporation

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ASIX ELECTRONICS CORPORATION
35
AX88796BLF / AX88796BLI
5.1.1 Command Register (CR)
Offset 00H (Read/Write)
Field
Name
Description (Default = 21h)
7:6
PS1, PS0 PS1, PS0: Page Select
The two bits select which register’s page is to be accessed.
It will be reset to default value when set PMR to D1 to D2 sleep state.
PS1
PS0
0
0
page 0 (default)
0
1
page 1
1
0
page 2
1
1
page 3
5:3
RD2,
RD1,
RD0
RD2, RD1, RD0: Remote DMA Command
These three encoded bits control operation of the Remote DMA channel. RD2 could be set
to abort any Remote DMA command in process. RD2 is reset by AX88796B when a
Remote DMA has been completed. The Remote Byte Count should be cleared when a
Remote DMA has been aborted. The Remote Start Address is not restored to the starting
address if the Remote DMA is aborted.
It will be reset to default value when set PMR to D1 to D2 sleep state.
RD2
RD1
RD0
0
0
0
Not allowed
0
0
1
Remote Read
0
1
0
Remote Write
0
1
1
Not allowed
1
X
X
Abort / Complete Remote DMA (default)
2
TXP
TXP: Transmit Packet
This bit could be set to initiate transmission of a packet
1
START
START:
This bit is used to active AX88796B operation.
This bit always read high when Host set once. It only clear by hardware or software reset.
0
STOP
STOP: Stop AX88796B
This bit is used to stop the AX88796B operation.
It will be reset to default value when set PMR to D1 to D2 sleep state.



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