AX88796BLF datasheet(20/82 Pages) ASIX

20 / 82 page

ASIX ELECTRONICS CORPORATION

AX88796BLF / AX88796BLI

Transmit Packet Assembly Format

The following diagrams describe the format for how packets must be assembled prior to transmission for different

byte ordering schemes. The various formats are selected in the Data Configuration Register.

D15

D[15:8]

D[7:0]

Destination Address 1

Destination Address 0

Destination Address 3

Destination Address 2

Destination Address 5

Destination Address 4

Source Address 1

Source Address 0

Source Address 3

Source Address 2

Source Address 5

Source Address 4

Type / Length 1

Type / Length 0

Data 1

Data 0

…

WTS = 1 in Data Configuration Register.

This format is used with ISA or 80186 Mode.

Destination Address 0 (DA0)

Destination Address 1 (DA1)

Destination Address 2 (DA2)

Destination Address 3 (DA3)

Destination Address 4 (DA4)

Destination Address 5 (DA5)

Source Address 0 (SA0)

Source Address 1 (SA1)

Source Address 2 (SA2)

Source Address 3 (SA3)

Source Address 4 (SA4)

Source Address 5 (SA5)

Type / Length 0

Type / Length 1

Data 0

Data 1

…

WTS = 0 in Data Configuration Register.

This format is used with ISA or MCS-51 Mode.

Note: All examples above will result in a transmission of a packet in order of DA0 (Destination Address 0), DA1,

DA2, DA3 and so on in byte. Bits within each byte will be transmitted least significant bit first.

AX88796BLF 数据表(PDF) 20 Page - ASIX Electronics Corporation

AX88796BLF 数据表(HTML) 20 Page - ASIX Electronics Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82

数据表下载