AX88796BLF datasheet(46/82 Pages) ASIX

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ASIX ELECTRONICS CORPORATION

AX88796BLF / AX88796BLI

5.1.52 Wakeup Frame Offset (WFOFST)

Page3 Offset 07H (Read/Write)

Field

Name

Description (Default = 00h)

7:0

WF0OFST Byte mask Offset for wake-up frame filter 0. Host continue write 4 times to completed

32-bits of Byte Mask 3, 2, 1, 0 Offset. The unit is 16-bit. (2bytes)

15:8

WF1OFST Byte mask Offset for wake-up frame filter 1.

23:16

WF2OFST Byte mask Offset for wake-up frame filter 2.

31:24

WF3OFST Byte mask Offset for wake-up frame filter 3.

5.1.53 Wakeup Frame Last Byte (WFLB)

Page3 Offset 08H (Read/Write)

Field

Name

Description (Default = 00h)

7:0

WFLB0

Mask Last Byte for wake-up frame filter 0. Host continue write 4 times to completed

32-bits of Last Byte of 3, 2, 1, 0 filter.

15:8

WFLB1

Mask Last Byte for wake-up frame filter 1.

23:16

WFLB2

Mask Last Byte for wake-up frame filter 2.

31:24

WFLB3

Mask Last Byte for wake-up frame filter 3.

5.1.54 Wakeup Frame Command (WFCMD)

Page3 Offset 09H (Read/Write)

Field

Name

Description (Default = 00h)

3:0

WFCMD0 Byte Mask Command for wake-up frame filter 0. Host continue write 4 times to completed

32-bits of Byte Mask Command of 3, 2, 1, 0 filter and Mask cascade commend.

Bit0: wake-up frame filter enable

Bit1: destination match enable

Bit2: Multicast match enable

Bit3: Reserved

7:4

WFCMD1 Byte Mask Command for wake-up frame filter 1.

11:8

WFCMD2 Byte Mask Command for wake-up frame filter 2.

15:12

WFCMD3 Byte Mask Command for wake-up frame filter 3.

19:16

WFCSCD

Byte Mask Cascade Command for wake-up frame filter

Bit-0: cascade wake-up filter 1 and 0

Bit-1: cascade wake-up filter 2 and 1

Bit-2: cascade wake-up filter 3 and 2

31:18

Reserved. Always zero.

5.1.55 Wakeup Control and Status Register (WUCSR)

Page3 Offset 0AH (Read/Write)

Field

Name

Description (Default = 00h)

Reserved

LSC

Link status change event flag. This bit will be clear when Host write PMR or set this bit.

WUFR

Wake-up Frame Received event flag. This bit will be clear when Host write PMR or set

this bit.

MPR

Magic Packet Received event flag. This bit will be clear when Host write PMR or set this

bit.

Reserved

LSCWE

Link status change wakeup enable

0: disable (Default)

1: enable

WUEN

Wake-up frame enable

0: disable (Default)

1: enable

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