AX88796BLF datasheet(37/82 Pages) ASIX

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ASIX ELECTRONICS CORPORATION

AX88796BLF / AX88796BLI

5.1.8 Number Of Collisions Register (NCR)

Page0 Offset 05H (Read)

Field

Name

Description (Default = 00h)

7:4

Always zero

3:0

NCR

If no collisions are experienced during a transmission attempt, the COL bit of the TSR will

not be set and the contents of NCR will be zero. If there are excessive collisions, the ABT bit

in the TSR will be set and the contents of NCR will be zero. The NCR is cleared after the

TXP bit in the CR is set.

5.1.9 Transmit Byte Count Register (TBCR1)

Page0 Offset 06H (Write)

Field

Name

Description

7:0

TBCR1

Transmit Byte Count Register.

5.1.10 Current Page Register (CPR)

Page0 Offset 06H (Read)

Field

Name

Description (Default = 4Dh)

7:0

CPR

The Buffer Management Logic as a backup register for reception uses this register

internally. CURR contains the address of the first buffer to be used for a packet reception

and is used to restore DMA pointers in the event of receive errors. This register is initialized

to the same value as PSTART and should not be written to again unless the controller is

Reset.

5.1.11 Interrupt Status Register (ISR)

Page0 Offset 07H (Read/Write)

Field

Name

Description (Default = 80h)

RST

Reset Status:

Set when AX88796B enters reset state (or a wake-up event) and cleared when a start

command is issued to the CR. Writing to this bit is no effect.

RDC

Remote DMA Complete

Set when remote DMA operation has been completed. Write this bit to high then reset it.

CNT

Counter Overflow

Set when MSB of one or more of the Tally Counters has been set. Write this bit to high

then reset its.

OVW

OVERWRITE: Set when receive buffer ring storage resources have been exhausted.

Write this bit to high then reset it.

TXE

Transmit Error

Set when packet transmitted with one or more of the following errors

Excessive collisions, Transmit over size and late collision.

Write this bit to high then reset it.

RXE

Receive Error

Indicates that a packet was received with one or more of the following errors

CRC error

Frame Alignment Error

Missed Packet

Write this bit to high then reset it.

PTX

Packet Transmitted

Indicates packet transmitted with no error

Write this bit to high then reset it.

PRX

Packet Received

Indicates packet received with no error.

Write this bit to high then reset it.

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