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ADL6331ACCZB-R7 数据表(PDF) 28 Page - Analog Devices

部件名 ADL6331ACCZB-R7
功能描述  0.38 GHz to 15 GHz TxVGA
PDF  54 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADL6331ACCZB-R7 数据表(HTML) 28 Page - Analog Devices

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Data Sheet
ADL6331
PROGRAMMABILITY GUIDE
analog.com
Rev. B | 28 of 54
The register map can be subdivided into the seven functional
groups, as shown in Table 7. See the Register Summary section for
a complete list of all the registers on the ADL6331.
Table 7. Memory Map Functional Groups
Register Address
Functional Blocks
0x000 to 0x011
SPI configuration
0x100 to 0x101
Function enable
0x104 to 0x109
AMP1 performance trimming and tuning
0x10A to 0x10D
RF path 4 preconfigurations: AMP1, AMP2,
Fixed gain/Bypass, DSA attenuation
0x10F to 0x115
AMP2 performance trimming and tuning
0x120 to 0x121
Auxiliary mux selection (Debug only), SPI
supply control
Table 7. Memory Map Functional Groups (Continued)
Register Address
Functional Blocks
0x140 to 0x145
FUSE space. Read only. Trimmed
parameters for AMP1 and AMP2 are stored.
FUNCTION AND SIGNAL PATH ENABLE
The enable bits for each circuit block are in Registers 0x100 and
0x101 (Table 8 and Table 9, respectively). Figure 93 shows a
breakdown of the individual blocks highlighted in red that have
corresponding enable controls in Register 0x100 and 0x101. The
ENP pin is a primary enable pin for the ADL6331 and is active high.
The bits in the enable registers can be configured independently of
the state of the ENP pin.
Figure 93. Signal Path Enable Block Diagram
Table 8. Register 0x100: Enable Register for MUX and LDO
Bits
Bit Name
Description
Reset
Access
[7:5]
RESERVED
Reserved.
0x0
R
4
AMUX_BG_EN
AMUX Bandgap Enable. If MUXOUT (Pin 7) is not used, set to 0.
0x1
R/W
0: Disable AMUX Bandgap.
1: Enable AMUX Bandgap.
3
RESERVED
Reserved.
0x0
R
2
RESERVED
Reserved.
0x0
R/W
1
RESERVED
Reserved.
0x0
R
0
LDO18_EN
1.8 V LDO Enable for AMUX Block. If MUXOUT (Pin 7) is not used, set to 0.
0x1
R/W
0: Disable.
1: Enable.
Table 9. Register 0x101: Enable Register for AMP1/AMP2 and DSA
Bits
Bit Name
Description
Reset
Access
[7:3]
RESERVED
Reserved.
0x0
R
2
AMP2_EN
AMP2 Enable.
0x0
R/W
0: Disable.
1: Enable.
1
RESERVED
DSA Enable.
0x0
R/W
0: Disable.
1: Enable.
0
LDO18_EN
AMP1 Enable.
0x0
R/W
0: Disable.
1: Enable.



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