Data Sheet

ADL6331

SPECIFICATIONS

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Rev. B | 9 of 54

Table 3. SPI Timing Specifications (Continued)

Parameter

Description

Min

Typ

Max

Unit

tDS

Setup time between data and rising edge of SCLK

10

ns

tDH

Hold time between data and rising edge of SCLK

5

ns

tDCS

Setup time between falling edge of CSB and SCLK

10

ns

tDV

Maximum time delay between falling edge of SCLK and output data valid for a read operation

10

ns

SPI Timing Diagrams

Figure 2. SPI Register Timing, MSB First

Figure 3. Timing Diagram for the SPI Register Write (3- and 4-Wire SPI Mode)

Figure 4. Timing Diagram for SPI Register Read (4-Wire SPI Mode)

Figure 5. Timing Diagram for SPI Register Read (3-Wire SPI Mode, SDIO Pin Is Bidirectional Mode, Input (Write) and Output (Read))