Data Sheet

ADL6331

SERIAL PORT INTERFACE (SPI)

analog.com

Rev. B | 34 of 54

INITIALIZATION SEQUENCE

The ADL6331 has a built-in initialization sequence that is triggered

by a software reset to correctly load data from the NVM into the

memory for normal amplifier operation. The calibrated and trimmed

settings for AMP1 and AMP2 are factory programmed and stored

in NVM prior to shipping to the user. After a software reset is

performed, the data in the NVM needs to be loaded into the

digital Register 0x140 to Register 0x145 for operation. This loading

process takes four SPI cycles, write or read, after the software reset

is asserted. The loading process is independent of the state of the

ENP pin, high or low.

The full procedure for initializing the part is as follows:

1. Supply 3.3 V.

2. Apply software reset.

3. Send four SPI commands to ADL6331 (read or write).

The software reset, sending 0x81 in Register 0x000, is always

recommended immediately after the 3.3 V is supplied.

After the 3.3 V is supplied, perform the following steps as shown in

Table 17):

1. Write 0x81 in Register 0x000 for the software reset.

2. Write 0x18 in Register 0x000 for configuring 4-wire SPI mode.

3. Write 0x01 in Register 0x00A1.

4. Write 0x02 in Register 0x00A.

5. Write 0x03 in Register 0x00A.

6. Write 0x07 in Register 0x101 to enable the AMP2, DSA, and

AMP1 to start the normal amplifier operation.

After four write cycles are sent, the data in Register 0x140 to

Register 0x145 are correctly loaded for use in operation.

Table 17 is the basic sequence to start ADL6331 in normal opera-

tion. After the sequence is complete, the registers are set to the

default configuration. It is recommended to enable AMP2, DSA, and

AMP1 (in Register 0x101) in the last SPI cycle (Step 6) to avoid any

unexpected output signals from the ADL6331 when the ENP pin is

set to high combined with the 3.3 V supply.

Table 17. Example 1: SPI Command Writes

Address

Write Data

Notes

0x000

0x81

Software reset

0x000

0x18

1st Cycle: Configure 4-wire SPI mode

0x00A

0x01

2nd Cycle: Scratch pad writing. Any data is fine.

0x00A

0x02

3rd Cycle: Scratch pad writing. Any data is fine.

0x00A

0x03

4th Cycle: Scratch pad writing. Any data is fine.

0x101

0x07

The data in Register 0x140 to Register 0x145 are correctly loaded to use for operation. Enable AMP2, DSA,

and AMP1 functions to start operations. Default register values are used for RF performance.

1 Register 0x00A is named Scratch Page and is a read and write register for SPI communication testing that does not affect performance in the ADL6331.