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Data Sheet

ADL6331

SERIAL PORT INTERFACE (SPI)

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Rev. B | 33 of 54

The SPI of the ADL6331 allows the user to configure the device for

specific functions or operations via 3- or 4-wire SPI mode. This seri-

al port interface consists of four control lines: SCLK, SDIO, SDO,

and CSB for 4-wire SPI mode. SCLK, SDIO, and CSB are used for

3-wire SPI mode, which is the default state for the SPI mode. To

enable 4-wire SPI mode, SDOACTIVE[3] and SDOACTIVE_[4] in

SPI port are shown in Table 3.

The ADL6331 protocol consists of a read/write bit, four chip ad-

dress bits (MSB is always 0), and nine register address bits,

followed by eight data bits. Both the address and data fields are

organized with the MSB first and end with the LSB by default.

To address the device correctly, the chip address prefix bits must

match the externally configured chip address Pin CA2, Pin CA1,

and Pin CA0.

The ADL6331 input logic levels to write to the SPI are 1.8 V or 3.3

On a readback cycle, the SDO is configurable for either

1.8 V (default) or 3.3 V readback output levels by setting

SPI_1P8_3P3_CTRL bit (Register 0x121, Bit 4).

CONFIGURING MULTIPLE CHIPS TO SHARE

THE SPI BUS

Up to eight ADL6331 devices can be addressed with the same 3-

or 4-wire SPI by using a single CSB line for all devices. For this

capability, the chip address pins (Pin CA2, Pin CA1, and Pin CA0)

of the ADL6331 are used to identify the chip with the SPI write chip

address prefix (see the SPI interface port as shown in Figure 2).

The ADL6331 ignores any writes to addresses where the four

MSBs are not equal to the chip address as set by the chip address

pins, and the device only accepts access for addresses where the

four MSB chip address prefix bits are equal to the chip address

pins. The only exception is the software reset in the address 0x000.

All ADL6331 chips on the shared bus accept 0x81 software reset in

0x000 register from the SPI host controller.

Figure 94 shows how to configure the chip address Pin CA2, Pin

CA1, and Pin CA0 with the associated chip address prefix bits.

Figure 94. Multiple Chip Configuration to Share SPI Bus

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