ADS5271 datasheet(16/42 Pages) TI2

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ADS5287

SBAS428D – JANUARY 2008 – REVISED JUNE 2012

www.ti.com

Table 3. SUMMARY OF FUNCTIONS SUPPORTED BY SERIAL INTERFACE(1) (2) (3) (4) (continued)

ADDRESS

IN HEX

D15

D14

D13

D12

D11

D10

NAME

DESCRIPTION

DEFAULT

Single-

DIFF_CLK

Differential clock mode.

ended clock

Enables the duty-cycle correction

EN_DCC

Disabled

circuit.

External

Drives the external reference

reference

EXT_REF_VCM

mode through the VCM pin.

drives REFT

and REFB

Controls the phase of LCLK

PHASE_DDR<1:0>

90 degrees

output relative to data.

PAT_DESKEW

Enables deskew pattern mode.

Inactive

PAT_SYNC

Enables sync pattern mode.

Inactive

Binary two's complement format

Straight

BTC_MODE

for ADC output.

offset binary

Serialized ADC output comes

LSB-first

MSB_FIRST

out MSB-first.

output

Enables SDR output mode

DDR output

EN_SDR

(LCLK becomes a 12x input

mode

clock).

Controls whether the LCLK rising

Rising edge

or falling edge comes in the

of LCLK in

FALL_SDR

middle of the data window when

middle of

operating in SDR output mode.

data window

SUMMARY OF FEATURES

POWER IMPACT (relative to default)

FEATURES

DEFAULT

SELECTION

AT fS = 65MSPS

ANALOG FEATURES

Internal or external reference

Internal reference mode takes approximately 23mW more power on

N/A

(driven on the REFT and REFB pins)

AVDD

External reference driven on the VCM pin

Off

Approximately 9mW less power on AVDD

Duty cycle correction circuit

Off

Approximately 7mW more power on AVDD

With zero input to the ADC, low-frequency noise suppression causes

Low-frequency noise suppression

Off

digital switching at fS/2, thereby increasing LVDD power by

approximately 7mW/channel

Differential clock mode takes approximately 7mW more power on

Single-ended or differential clock

Single-ended

AVDD

Refer to the Power-Down Modes section in the Electrical

Power-down mode

Off

Pin and register 0F

Characteristics table

DIGITAL FEATURES

Programmable digital gain (0dB to 12dB)

0dB

Registers 2A and 2B

No difference

Straight offset or BTC output

Straight offset

No difference

Swap polarity of analog input pins

Off

No difference

LVDS OUTPUT PHYSICAL LAYER

LVDS internal termination

Off

Approximately 7mW more power on AVDD

LVDS current programmability

3.5mA

As per LVDS clock and data buffer current setting

LVDS OUTPUT TIMING

LSB- or MSB-first output

LSB-first

No difference

SDR mode takes approximately 2mW more power on LVDD

DDR or SDR output

DDR

(at fS = 30MSPS)

LCLK phase relative to data output

Refer to Figure 1

No difference

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